Sony HDVF-C30W Maintenance Manual page 22

(3) LCD bias signal system check
Connect an oscilloscope to TP31-48, TP59, TP89, TP90, and TP93 of the EX-909 board and confirm that
the output voltages meet the voltage values as described in table 1.
Table 1
TP No. TP name
101 _
102 _
103 _
1 GND
2 to 25
26 POL
27 REV
28 LS
29 TCK/BCK
30 GND
31 VH0 *1
34 VH3 *1
38 VH7 *1
39 VH8 *1
40 VL8 *1
41 VL7 *1
45 VL3 *1
48 VL0 *1
49 TLBR/BLBR
53 SP1
54 SP4
59 VLCO *2
61 GND
62 GND
63 GND
76 GND
87 DIO
88 FX
89 VOFF *2
VGG *2
90
93 VCCO *2
m
*1 : VH, VL: LCD S-shape characteristics and 2.2nd power characteristics correction bias
*2 : VLCO, VOFF, VGG, VCCO : Power supply for the source driver and gate driver.
*3 : 0- to 7-bit signal of Rch, Gch, and Bch signals that are sent to LCD.
TP2 to TP9 : 0- to 7-bit Rch signal
TP10 to TP17 : 0- to 7-bit Gch signal
TP18 to TP25 : 0- to 7-bit Bch signal
1-16 (E)
Function
Video signal (D/A output)
Video signal (D/A output)
Video signal (D/A output)
GND
*3
Video signal polarity inverted (L)
LCD drive polarity
(Inverted every H period))
LCD video output
H transfer clock
GND
+Gamma correction (9.5 V)
+Gamma correction (7.1 V)
+Gamma correction (5 V)
+Gamma correction (5 V)
_Gamma correction (4.8 V)
_Gamma correction (4.8 V)
_Gamma correction (2.8 V)
_Gamma correction (0.4 V)
H display is inverted
Normal : L/H, Inverted : H/L
H transfer starts during normal
mode
H transfer starts during inverted
mode
Source driver power supply
(10.5 V)
GND
GND
GND
GND
V transfer starts
V transfer clock
Gate bias (_7.2 V)
Gate bias (20 V)
Logic system power supply (3.1 V) VCCO
CN5 connection CN6 connection
Bch signal Rch signal
Gch signal Gch signal
Rch signal Bch signal
GND GND
POL POL
REV REV
LS LS
TCK BCK
GND GND
VH0 VH0
VH3 VH3
VH7 VH7
VH8 VH8
VL8 VL8
VL7 VL7
VL3 VL3
VL0 VL0
TLBR BLBR
SP1 SP4
SP4 SP1
VLCO VLCO
GND GND
GND GND
GND GND
GND GND
DIO GND
FX GND
VOFF GND
VGG GND
VCCO
HDVF-C30W