Figure 29 D20S Digital Input Peripheral Block Diagram - GE D20 Technical Overview

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millisecond and placed in a first in - first out (FIFO) buffer for transmission to the D20 main
processor. Refer to Figure 29.
Time-tagged changes are reported in chronological order. Non-time-tagged changes are placed in
a separate FIFO buffer and reported upon request. An anti-chatter filter function prevents one or
more chattering points from filling the FIFO buffer. Each COS and SOE FIFO buffer is 256
events long.
D20S Logic Section
Parallel
Peripheral
Interface
PPI

Figure 29 D20S Digital Input Peripheral Block Diagram

GE Information
Buffer, Opto
Input Voltage
Steering
Option
Interface
PRPI-019-3.00-10
D20/D200 Technical Overview
D20S Termination Board
SWC and
Impulse
Protection
Input
1 - 8
9 - 16
17 - 24
25 - 32
33 - 40
41 - 48
49 - 56
57 - 64
45