Brother HL-730Plus Service Manual page 21

<HL-730/730Plus>
Fig. 2.4 shows a block diagram of the main PCB.
A S I C
CPU Core
(MC68EC000)
Reset Circuit Oscillator (15.3MHz)
BUS INT
Address Decoder
DRAM Control
Program + Font ROM
512 Kbytes
Timer
RAM
(0.5 Mbytes)
FIFO
Option RAM
DATA EXTENSION
(1M or 1.5Mbytes)
To PC
CDCC Parallel I/O
Option Serial I/O
(RS232C & RS422A)
Soft Support
EEPROM (128 8 bits)
EEPROM I/O
Motor Driver
Engine Control I/O
To Panel Sensor PCB
Fig. 2.4
II-4