Watchdog Timer Initial Program - Efco EBC-3330 User Manual

B.1 Watchdog Timer Initial Program
CR F0h. Watchdog Timer I(WDT1) and KBC P20 Control Mode Register
Location: Address F0h
Attribute: Read/Write
Power Well: VCC
Reset by: LRESET# or PWROK
Default: 00h
Size: 8 bits
BIT READ / WRITE
7-5 Reserved.
4 R / W
3 R / W
2 R / W
1 R / W
0 Reversed
Table_51 – CR F0h. Watchdog Timer I(WDT1) and KBC P20 Control Mode Register
CR F1h. Watchdog Timer I(WDT1) Counter Register
Location: Address F1h
Attribute: Read/Write
Power Well: VCC
Reset by: LRESET# or PWROK
Default: 04h
Watchdog Timer I count mode is 1000 times faster.
0: Disable.
1: Enable.
(If bit-3 is 0, the count mode is 1/1000 seconds mode.)
(If bit-3 is 1, the count mode is 1/1000 minutes mode.)
Select Watchdog Timer I count mode.
0: Second Mode.
1: Minute Mode.
Enable the rising edge of a KBC reset (P20) to issue a time-
out event.
0: Disable.
1: Enable.
Disable / Enable the Watchdog Timer I output low pulse to
the KBRST# pin (PIN59)
0: Disable.
1: Enable.
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