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Size: 8 bits
BIT
READ / WRITE
7-0
R / W
CR F2h. Watchdog Timer I(WDT1) Control & Status Register
Location: Address F2h
Attribute: Read/Write
Power Well: VCC
Reset by: LRESET# or PWROK
Default: 00h
Size: 8 bits
BIT
READ / WRITE
7
R / W
6
R / W
5
Write "1" Only Trigger Watchdog Timer I event. This bit is self-clearing.
R / W
4
Write "0" Clear
3-0
R / W
Table_53 – CR F2h. Watchdog Timer I(WDT1) Control & Status Register
DESCRIPTION
Watch Dog Timer I Time-out value. Writing a non-zero value
to this register causes the counter to load the value into the
Watch Dog Counter and start counting down. If CR F2h, bits
7 and 6 are set, any Mouse Interrupt or Keyboard Interrupt
event causes the previously-loaded, non-zero value to be
reloaded to the Watch Dog Counter and the countdown
resumes. Reading this register returns the current value in
the Watch Dog Counter, not the Watch Dog Timer Time-out
value.
00h: Time-out Disable
01h: Time-out occurs after 5.03x107 CLKIN cycle time, by
analogy. (5.03x107x (1/48MHz) = 1.046s)
Table_52 – CR F1h. Watchdog Timer I(WDT1) Counter Register
DESCRIPTION
Mouse interrupt reset enables watch-dog timer reload
0: Watchdog Timer I is not affected by mouse interrupt.
1: Watchdog Timer I is reset by mouse interrupt.
Keyboard interrupt reset enables watch-dog timer reload
0: Watchdog Timer I is not affected by keyboard interrupt.
1: Watchdog Timer I is reset by keyboard interrupt.
Watchdog Timer I status bit
0: Watchdog Timer I is running.
1: Watchdog Timer I issues time-out event.
These bits select the IRQ resource for the Watchdog Timer I
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