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2 Design-in
2.1 Design guidelines
2.1.1 Module supply (VCC) design
Good connection of the module's VCC pin with DC supply source is required for correct RF performance. The
guidelines are summarized below:
•
VCC connection must be as wide and short as possible.
•
Any series component with Equivalent Series Resistance (ESR) greater than few milliohms must be
avoided.
•
The VCC connection must be routed through a PCB area separated from sensitive analog signals and
sensitive functional units. It is a good practice to interpose at least one layer of PCB ground between
VCC track and other signal routing.
There is no strict requirement of adding bypass capacitance to the supply net close to the module. But
depending on the layout of the supply net and other consumers on the same net, bypass capacitors might still
be beneficial. Though the GND pins are internally connected, connect all the available pins to solid ground on
the application board, as a good (low impedance) connection to an external ground can minimize power loss
and improve RF and thermal performance.
2.1.2 Generic digital interfaces supply output (V_INT) design
The ODIN-W2 series modules provide a 1.8 V supply rail output through the V_INT pin. The same voltage
domain is used internally to supply the generic digital interfaces of the modules. The V_INT supply output can be
used for interface logic. The External digital interface logic should have decoupling on the supply pins according
to the respective datasheet.
•
Do not apply loads, which might exceed the limit for maximum available current from V_INT supply (see
the ODIN-W2 series Data Sheet [2]) as this can cause malfunctions in internal circuitry.
•
Since the V_INT supply is generated by an internal switching step-down regulator, it is not
recommended to supply sensitive analog circuitry without adequate filtering for digital noise.
•
V_INT can only be used as an output. Do not connect any external supply source on V_INT.
•
ESD sensitivity rating of the V_INT supply pin is 1 kV (Human Body Model according to JESD22-A114).
•
Higher protection level could be required if the line is externally accessible and it can be achieved by
mounting an ESD protection (for example, EPCOS CA05P4S14THSG varistor array) close to the
accessible point.
See Schematic for ODIN-W2 section for V_INT design examples.
2.1.3 Low power clock (LPO_CLK) design
The LPO_CLK input pin requires accurate layout design. Avoid injecting noise on these pins as it may affect the
stability of the LPO timing reference. See the Schematic for ODIN-W2 section for additional information.
2.1.4 Asynchronous serial interface (UART) design
The layout of the UART bus should be done so that noise injection and cross talk are avoided. See the Schematic
for ODIN-W2 section for additional information.
2.2 Antenna interface design
As the unit cannot be mounted arbitrary, the placement should be chosen with consideration so that it does not
interfere with radio communication. The ODIN-W262 with an internal surface mounted antenna cannot be
mounted in a metal enclosure. No metal casing or plastics using metal flakes should be used. Avoid metallic
based paint or lacquer as well.
UBX-14040040 - R03
ODIN-W2 series - System Integration Manual
Advance Information
Design-in
Page 14 of 33
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