Block Diagram - Video Processor Section - Sony STR-DA5500ES Service Manual Digest

Q Q
3 7 6 3 1 5 1 5 0
5-6.

BLOCK DIAGRAM - VIDEO PROCESSOR Section -

Q[2] – Q[11],
Q[14] – Q[23],
30
Q[26] – Q[35]
32
D-VIDEO BUS1
(Page 25)
RX_ODCK[1]
RX_HSYNC
RX_VSYNC
RX_DE
12
D-VIDEO BUS3
D[2] – D[11],
(Page 26)
D[14] – D[23],
30
D[26] – D[35]
FLI_ODCK
FLI_HSYNC
FLI_VSYNC
SD-RAM
FLI_DE
IC3618
DATA BUS
DQ0 – DQ15 FSDATA [16] – FSDATA [31]
T E
L 1 3 9 4 2 2 9 6 5 1 3
ADDRESS BUS
A0 – A12 FSADD [0] – FSADD [12]
CLK 45
46
/CLK
44
CKE
BA0 26
BA1 27
CS 24
23
RAS
22
CAS
WE 21
LDM 20
UDM 47
16
LDQS
51
UDQS
SD-RAM
IC3602
DATA BUS
DQ0 – DQ15
FSDATA [0] – FSDATA [15]
ADDRESS BUS
A0 – A12
FSADD [0] – FSADD [12]
CLKP
CLK
45
CLKN
/CLK 46
CKE
CKE 44
FSBKSEL0
BA0 26
FSBKSEL1
BA1
27
FSCS0
CS
24
RAS
RAS 23
CAS
CAS 22
WE
WE 21
w w w
LDM
20
UDM
47
LDQS 16
UDQS 51
STR-DA5500ES
VIDEO PROCESSOR
IC3601
A2P AF1 CR
70
B2P AE2 CB
(Page 30)
C2P AF2 Y/G
CVBS
A3P AF4
EXT_IN
B3P AE5
38
C1P AC1 CY
P4 IPCLK1
(Page 33)
CB
B1P AC2
Y1 AHS
AVS
Y2 A1P AB1 CR
Y3 AHREF_DE
X3602
TCLK C26
19.6608MHz
MSTR0_SDA AA23 5 SDA EEPROM
MSTR0_SCL AA24 6 SCL IC3621
P24 DCLK
SV1P AB2
SV2P AE1
SV3P AE4
P25 DHS
R26 DVS
AIP_RAW_HS_CS AF12
P26 DEN
AIP_RAW_VS AE12
FSDATA16 –
FSDATA31
FSADDR0 –
FSADDR12
D5 FSCLKP
C5 FSCLKN
C4 FSCKE
C21 FSBKSEL0
C20 FSBKSEL1
D21 FSCS0
C24 FSRAS
D24 FSCAS
C23 FSWE
B22 FSDQM3
B17 FSDQM2
A22 FSDQS3 FLASH MEMORY
IC3615
A17 FSDQS2
OCMDATA0 –
F_D [0] – F_D [15] DQ0 – DQ15
OCMDATA15
OCMADDR1 –
F_A [1] – F_A [21] A0 – A20
OCMADDR21
ROM_CS_N AD24 26 CE
OCN_RE_N AC25 28 OE
OCN_WE_N AC26 11 WE
FSDATA0 –
FSDATA15
12 RESET
43 XI
X3603
4MHz
42 XO
A11 FSDQM1
A6 FSDQM0
RESET AD9 70 Faroudja UCOM RESET
x a o
B11 FSDQS1
y
MSTR1_SCL A3 72 Faroudja UCOM BUSY
B6 FSDQS0
MSTR1_SDA A2 71 Faroudja Power DETECT
. i
OCM_UDI_1 B3 150 Faroudja UCOM UART TX
OCM_UDO_1 B2 151 Faroudja UCOM UART RX
LBADC_IN1 AF10 73 MAIN Faro wake
OCM_UDI_0 W25
OCM_UDO_0 W26
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8
OSD CONTROLLER
IC3604
FLASH MEMORY
103 R
IC3603
104 G
DATA BUS
105
B
MD0 – MD15 Y_D [0] – Y_D [15] DQ0 – DQ15
ADDRESS BUS
137 HDMI SYS +3.3V
HSYNC_N
MA1 – MA24 Y_A [0] – Y_A [23]
136 A0 – A23
VSYNC_N
Q Q OE REFERENCE
MOE_N 74 34
3 7 6 3
VOLTAGE
WE
MWE_N 73 13
REGULATOR
14 RESET
Q001, 002
D0 – D7 PS0 – PS2
23 25 39 28 29 30 33 – 31
15 – 22
YAMAHA_D [0] – YAMAHA_A [0] –
YAMAHA_D [7] YAMAHA_A [2]
BUFFER BUFFER
IC3620 IC3619
DIR XOE XOE
1 19 19
96 56 67 106 – 121 87 122 – 131, 134 – 141
u 1 6 3
.
VIDEO SYSTEM CONTROLLER
IC3610 (3/3)
27 27
2 4
9 9
D/A CONVERTER
IC3850
D[16] - D[23],
16
D[28] - D[35]
Y0 – Y7,
C0 – C7
FLI_HSYNC
23 P_HSYNC
50 S_HSYNC
FLI_VSYNC
24 P_VSYNC
49 S_VSYNC
FLI_DE
25 P_BLANK
48 S_BLANK
FREQUENCY
MULTIPLIER
IC3854
FLI_ODCK
2 IN OUT2 8 32 CLKIN_A
FS1
5
33
1 5 1 5 0 8 9 2
106
141
XIN
X3601
33.2MHz
XOUT 142
S-RAM
IC3611
WE UB LB OE CE
17 40 39 41 6
3 8 11
AND
GATE
IC3609
1 2 10 9 12 13
95 94 93 86 171 169 174 175
m
c o
MAIN UCOM BUSY
STR-DA5500ES
2
8 9 9
V 44 CVBS OUT1
Y/G 39 CY OUT1
41
CB/R 38 CB OUT1
(Page
CR/B 37 CR OUT1 33)
21 22
UC3V_SDA,
UC3V_SCL
33
(Page
25)
4 9 8 2 9 9
SIGNAL PATH
: VIDEO
RX232C
30
TX232C
(Page
24)
DATA SELECTOR
IC3630
0X 13
13 X-COM 1X 14
3 Y-COM 0Y 1
1Y 5
A B
10 9
51
NON_LPCM
NON LPCM 45
(Page
Flash Update Rx 54
22)
Flash Update Tx 53
VIDEO_UCOM_SDA
MAIN UCOM SDA 162
MAIN UCOM SCL 164 VIDEO_UCOM_SCL
163 VUCOM_BUSY
26
STOP IN 157 STOP
ENDFLAG 52 VUCOM_FLG
(Page
VUCOM_MD
MD0 40 34)
INIT 39 VUCOM_RST