Sony DSR-DR1000 Service Manual page 63

TSB43AB22 (TI)
TSB43AB22APDT
IEEE1394A OHCI PHYSICAL / LINK-LAYER CONTROLLER
—TOP VIEW—
97
100
105
110
115
120
125
128
INPUTS
CPS : CABLE POWER STATUS
G RST
: GLOBAL POWER RESET
PC0 - PC2 : POWER CLASS PROGRAMMING
PCI CLK : PCI BUS CLOCK
PCI GNT
: PCI BUS GRANT
PCI IDSEL : INITIALIZATION DEVICE SELECT
PCI RST
: PCI RESET
REG EN
: REGULATOR ENABLE
OUTPUTS
CINT
: CARD BUS INTERRUPT
CSTSCHG : CARD STATUS CHANGE
PCI INTA
: INTERRUPT
PCI PME
: POWER MANAGEMENT EVENT
PCI REQ
: PCI BUS REQUEST
PCI SERR
: PCI SYSTEM ERROR
INPUTS/OUTPUTS
BE0 BE3
- : BYTE ENABLE
CARDBUS
: CARD BUS CIS BASE ADDRESS REGISTER SELECT
CNA : CABLE NOT ACTIVE
CYCLEIN, CYCLEOUT : CYCLE TIMER SYNCRONIZATION
FILTER0, FILTER1 : PLL FILTER
GPIO2, GPIO3 : GENERAL PURPOSE I/O
PCI AD0 - PCI AD31 : PCI ADDRESS/DATA BUS
PCI C : PCI BUS COMMAND
PCI CLKRUN
: CLOCK RUN
PCI DEVSEL
: PCI DEVICE SELECT
PCI FRAME
: PCI CYCLE FRAME
PCI IRDY
: PCI INITIATOR READY
PCI PAR : PCI PARITY
PCI PERR
: PCI PARITY ERROR INDICATOR
PCI STOP
: PCI SYCLE STOP
PCI TRDY
: PCI TARGET READY
SCL : SERIAL CLOCK
SDA : SERIAL DATA
TEST0 - TEST3, TEST8, : TEST
TEST9, TEST16, TEST17
TPA0+, TPA1+, : TWISTED-PAIR CABLE
TPA0_, TPA1_,
TPB0+, TPB1+,
TPB0_, TPB1_
TPBIAS0, TPBIAS1 : TWISTED-PAIR BIAS
OTHERS
R0, R1 : CURRENT SETTING RESISTER
REG18 : 1.8 V POWER SUPPLY FOR DEVICE CORE
V : PCI SIGNALING CLAMP VOLTAGE POWER
CCP
XI, XO : CRYSTAL OSCILLATOR
DSR-DR1000/DR1000P
PIN
NO.
1
64 2
3
60 4
5
6
55
7
8
50
9
10
11
45
12
13
40
14
15
16
35
17
33
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PCI
HOST
BUS
INTERFACE
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
— A.V 33 — D.GND 65
CC
BE3
— A.V 34 I/O PCI C/ 66
CC
I/O FILTER0 35 — V 67
CCP
I/O FILTER1 36 I PCI IDSEL 68
— XI 37 I/O PCI AD23 69
— XO 38 I/O PCI AD22 70
— PLLV 39 — D.V 71
CC CC
— PLLGND 40 I/O PCI AD21 72
REG EN
I 41 I/O PCI AD20 73
I/O TEST17 42 I/O PCI AD19 74
I/O TEST16 43 I/O PCI AD18 75
PCI CLKRUN
I/O 44 — D.GND 76
PCI INTA CINT
O / 45 I/O PCI AD17 77
G RST
I 46 I/O PCI AD16 78
BE2
— D.V 47 I/O PCI C/ 79
CC
I PCI CLK 48 — VCCP 80
PCI FRAME
— D.GND 49 I/O 81
PCI GNT PCI IRDY
I 50 I/O 82
PCI REQ
O 51 — D.V 83
CC
PCI TRDY
— V 52 I/O 84
CCP
PCI PME PCI DEVSEL
O /CSTSCHG 53 I/O 85
PCI STOP
I/O PCI AD31 54 I/O 86
— D.GND 55 — D.GND 87
PCI PERR
I/O PCI AD30 56 I/O 88
PCI SERR
I/O PCI AD29 57 O 89
I/O PCI AD28 58 I/O PCI PAR 90
— D.V 59 — D.V 91
CC CC
BE1
I/O PCI AD27 60 I/O PCI C/ 92
I/O PCI AD26 61 I/O PCI AD15 93
— REG18 62 — V 94
CCP
I/O PCI AD25 63 I/O PCI AD14 95
I/O PCI AD24 64 — D.GND 96
PCI
INITIAL
TARGET
REGISTERS
SM
ISOCHRONOUS
TRANSMIT
CONTEXTS
ASYNCHRONOUS
TRANSMIT
CONTEXTS
PHYSICAL DMA
AND RESPONSE
CENTRAL RESP
ARBITER
TIME-OUT
AND
PCI
INITIATOR
PHY
SM
REGISTER
ACCESS
AND
STATUS
MONITOR
REQUEST
FILTERS
GENERAL
REQUEST
RECEIVE
ASYNCHRONOUS
RESPONSE
RECEIVE
ISOCHRONOUS
RECEIVE
CONTEXTS
CABLE
PORT 0
CABLE
PORT 1
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND CLOCK
GENERATOR
PIN
I/O SIGNAL I/O SIGNAL
NO.
I/O PCI AD13 97 I PC2
I/O PCI AD12 98 I PC1
I/O PCI AD11 99 I PC0
— D.GND 100 — D.V
CC
I/O PCI AD10 101 I/O TEST3
I/O PCI AD9 102 I/O TEST2
I/O PCI AD8 103 — D.GND
— D.V 104 I/O TEST1
CC
BE0
I/O PCI C/ 105 I/O TEST0
I/O PCI AD7 106 I CPS
— D.GND 107 — A.V
CC
I/O PCI AD6 108 — A.V
CC
I/O PCI AD5 109 — A.GND
— V 110 — A.GND
CCP
I/O PCI AD4 111 — A.GND
I/O PCI AD3 112 I/O TPB0_
I/O PCI AD2 113 I/O TPB0+
I/O PCI AD1 114 I/O TPA0_
— D.GND 115 I/O TPA0+
I/O PCI AD0 116 I/O TPBIAS0
PCI RST
I 117 — A.GND
CARDBUS
I/O CYCLEOUT/ 118 — R0
I/O CYCLEIN 119 — R1
— D.V 120 — A.V
CC CC
I/O GPIO3 121 I/O TPB1_
I/O GPIO2 122 I/O TPB1+
I/O SCL 123 I/O TPA1_
I/O SDA 124 I/O TPA1+
— REG18 125 I/O TPBIAS1
I/O TEST9 126 — A.GND
I/O TEST8 127 — A.GND
I/O CNA 128 — A.GND
SERIAL
ROM
OHCI PCI POWER
MGMT AND CLKRUN
GPIOs
MISC
INTERFACE
TRANSMIT
FIFO
LINK
TRANSMIT
RECEIVE
ACKNOWLEDGE
CYCLE START
GENERATOR AND CRC
CYCLE MONITOR
SYNTHESIZED
BUS RESET
PHY/LINK
LINK
INTERFACE
RECEIVE
RECEIVE
FIFO
RECEIVED DATA
DECODER/RETIMER
ARBITRATION
AND CONTROL
STATE MACHINE
LOGIC
BIAS VOLTAGE
AND
CURRENT
GENERATOR
TRANSMIT DATA
ENCODER
7-13
IC