Fpga Configuration Registers Via Spi; Configuration Enhancements - Connect Tech Multi-I/O User Manual

Connect Tech - Xtreme/Multi-I/O - Users Guide

FPGA Configuration Registers via SPI

This information is mostly intended for developers of PIC32 software for the hardware of this board.
The configuration information is transferred from the PIC32 microcontroller to the FPGA via an SPI Bus interface.
That interface is setup with the PIC32 software. The clocking for the FPGA's SPI port (and other logic) is supplied
by the PIC32.
For setup purposes, these registers can be queried with the SPIR command (see the "Testing / Debugging" section
for a description of this command.

Configuration Enhancements

Relative to a competitor's product, our product offers configurations enhancements in these areas.

Any Port can be IO or Memory Space mapped.

Memory mapping extends to the full PC/104 Bus addressing range (24 bits).

IO decoding range extendable to 12 bits (0x000 to 0xFFF).

Additional IRQ selections.

CAN Port clock selections.

Board level "IO" Port for Resets, Interrupt Status and LED operations.

Comprehensive J1708 support via FPGA (additional J1708 Port).

RS485 options ( ½ Duplex, Termination).

5V or 3.3V Socket Module powering.
Document: CTIM-00116
Revision: 0.02
Page 40 of 50
Connect Tech Inc. Proprietary Information 0.02
Date: Apr. 14, 2015