Connect Tech Multi-I/O User Manual page 3

Connect Tech - Xtreme/Multi-I/O - Users Guide
Operation ..................................................................................................................................................... 30
Receiver ............................................................................................................................................ 30
Transmitter ........................................................................................................................................ 31
Detecting Transmission Errors or Potential Problems ............................................................................................... 31
Transmission Success ................................................................................................................................................... 31
J1708 Interrupts ............................................................................................................................... 32
Command, Control, Status Registers ...................................................................................................... 33
Command Register (Offset: 0x00) ................................................................................................. 33
Restart J1708 Bus SYNC .............................................................................................................................................. 33
Abort TX ........................................................................................................................................................................... 33
TX Kick ............................................................................................................................................................................. 33
Control Register (Offset: 0x01, Mem=0x04) ................................................................................ 34
Mask Reception of Good Transmitted Bytes .............................................................................................................. 34
TX Priority Register (Offset: 0x02) ................................................................................................................................ 34
TX Problem Limit Register (Offset: 0x03)..................................................................................... 34
J1708 Interrupt Status Register (Offset: 0x04) ............................................................................ 35
FIFO Status Register (Offset: 0x05) .............................................................................................. 35
RX EOM Level Register (Offset: 0x06) ......................................................................................... 36
RX Almost Full Level Register (Offset: 0x07) .............................................................................. 36
User-Ta Register (Offset: 0x08).................................................................................................... 37
Data FIFO's ....................................................................................................................................... 37
J1708 IO ....................................................................................................................................................... 37
IO Connector & Jumper Locations ................................................................................................. 38
Serial Port-8 to Module GPIO Configuration .................................................................................. 39
Location of Resistors .................................................................................................................................. 39
FPGA Configuration Registers via SPI ........................................................................................... 40
Configuration Enhancements ................................................................................................................... 40
FPGA Configuration Registers ................................................................................................................. 41
PORT_CONFIG[N] (Reg 0  10) .................................................................................................. 43
IRQ_CONFIG[N] (Reg 12  16) ................................................................................................... 46
MEM_CONFIG (Reg 17)................................................................................................................. 47
MISC_CONFIG (Reg 18) ................................................................................................................ 49
FPGA_VERSION (Reg 19)............................................................................................................. 50
Document: CTIM-00116
Revision: 0.02
Page 3 of 50
Connect Tech Inc. Proprietary Information 0.02
Date: Apr. 14, 2015