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STATIC MEMORY CONTROLLER
2 FEATURE
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Supports asynchronous static memory-mapped devices including RAM, ROM, OneNAND and flash
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Supports synchronous static memory-mapped devices including synchronous burst flash
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Supports asynchronous page mode read operation in non-clocked memory subsystems
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Supports asynchronous burst mode read access to burst mode ROM and flash devices
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Supports synchronous burst mode read, write access to burst mode ROM and flash devices
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Supports 8 and 16-bit data bus
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Address space : Up to 64MB per Bank
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Fixed memory bank start address
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External wait to extend the bus cycle
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Support byte, half-word and word access for external memory
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Programmable wait states, up to 31
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Programmable bus turnaround cycles, up to 15
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Programmable output enable and write enable delays, up to 15
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Configurable size at reset for boot memory bank using external control pins
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Support for interfacing to another memory controller using an External Bus Interface (EBI)
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Multiple memory clock frequencies available, HCLK and HCLK/2
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Eight word, 32-bit, wrapping reads from 16-bit memory
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SMBSTWAIT is synchronous burst wait input that the external device uses to delay a synchronous burst
transfer for bank 0. When this signal is not used, it shall be driven to high.
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nWAIT is wait mode input from external memory controller. Active HIGH or active LOW, as programmed in
the SMC Control Registers for each bank.
5-2
S3C2416X RISC MICROPROCESSOR
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