Synthesizer Operation - Motorola GM328 Service Manual

UHF (450-527 MHz) Frequency Synthesis
The external RX buffers (Q5332) are enabled by a high at U5201 pin 3 (AUX4) via transistor switch
Q5333. In TX mode the modulation signal (VCOMOD) from the LVFRAC-N synthesizer IC (U5201
pin41) is applied modulation circuitry CR5321, R5321, R5322 and C5324, which modulates the TX
VCO frequency via coupling capacitor C5321. Varactor CR5321 is biased for linearity from VSF.
4.4

Synthesizer Operation

The complete synthesizer subsystem comprises mainly of low voltage FRAC-N (LVFRACN) IC,
Reference Oscillator (crystal oscillator with temperature compensation), charge pump circuitry, loop
filter circuitry and DC supply. The output signal PRESC_OUT of the VCOBIC (U5301 pin 12) is fed
to pin 32 of U5201 (PREIN) via a low pass filter (C5229, L5225) which attenuates harmonics and
provides the correct level to close the synthesizer loop.
The pre-scaler in the synthesizer (U5201) is basically a dual modulus pre-scaler with selectable
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn
receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output
of the loop divider is connected to the phase detector, which compares the loop divider´s output
signal with the reference signal.The reference signal is generated by dividing down the signal of the
reference oscillator (Y5261 or Y5262).
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump.
The charge pump outputs a current at pin 43 of U5201 (IOUT). The loop filter (which consists of
R5221-R5223, C5221-C5225,L5221) transforms this current into a voltage that is applied to the
varactor diodes CR5311 for transmit, CR5301, CR5302 & CR5303 for receive and alters the output
frequency of the VCO .The current can be set to a value fixed in the LVFRAC-N IC or to a value
determined by the currents flowing into BIAS 1 (U5201-40) or BIAS 2 (U5201-39). The currents are
set by the value of R5251 or R5252 respectively. The selection of the three different bias sources is
done by software programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the
magnitude of the loop current is increased by enabling the IADAPT (U5201-45) for a certain
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high
transient of the CSX line. When the synthesizer is within the lock range the current is determined
only by the resistors connected to BIAS 1, BIAS 2, or the internal current source. A settled
synthesizer loop is indicated by a high level of signal LOCK (U5201-4).
The LOCK (U5201-4) signal is routed to one of the µP´s ADCs input U101-56. From the voltage the
µP determines whether LOCK is active. In order to modulate the PLL the two spot modulation
method is utilized. Via pin 10 (MODIN) on U5201 the audio signal is applied to both the A/D
converter (low freq path) as well as the balance attenuator (high freq path). The A/D converter
converts the low frequency analogue modulating signal into a digital code that is applied to the loop
divider, thereby causing the carrier to deviate. The balance attenuator is used to adjust the VCO's
deviation sensitivity to high frequency modulating signals. The output of the balance attenuator is
present at the MODOUT port (U5201-41) and connected to the VCO modulation diode CR5321 via
R5321, C5325.
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