Cpu Clock Source - Digilent Basys MX3 Reference Manual

Basys MX3™ Board Reference Manual
RPF4R = 0x01; // 0001 corresponds to U3TX
Input and output remapping is illustrated in the SPI2 section, where the SPI2 pins are mapped over the pins of
PMOD A connector.
1.5

CPU Clock Source

The PIC32 microcontroller supports numerous clock source options for the main processor operating clock. The
Basys MX3 uses an 8 MHz external crystal for use with the XT oscillator option. Oscillator options are selected via
the configuration settings specified using the #pragma config statement. Use #pragma config
POSCMOD=XT to select the XT option.
Using the internal system clock phase-locked loop (PLL), it is possible to select numerous multiples or divisions of
the 8 MHz oscillator to produce CPU operating frequencies up to 80 MHz. The clock circuit PLL provides an input
divider, multiplier, and output divider. The external clock frequency (8 MHz) is first divided by the input divider
value selected. This is multiplied by the selected multiplier value and then finally divided by the selected output
divider. The result is the system clock, SYSCLK, frequency. The SYSCLK frequency is used by the CPU, DMA
controller, interrupt controller, and pre-fetch cache.
The values controlling the operating frequency are specified using the PIC32MX370 configuration variables. These
are set using the #pragma config statement. Use #pragma config FPLLIDIV to set the input divider,
#pragma config FPLLMUL to set the multiplication factor, and #pragma config FPLLODIV to set the
output divider. Refer to the PIC32MX3XX/4XX Family Datasheet and the PIC32MX Family Reference Manual,
Section Oscillators, for information on how to choose the correct values, as not all combinations of multiplication
and division factors will work.
In addition to configuring the SYSCLK frequency, the peripheral bus clock, PBCLK, frequency is also configurable.
The peripheral bus clock is used for most peripheral devices; particularly the clock used by the timers and serial
controllers (UART, SPI, I2C). The PBLCK frequency is a division of the SYSCLK frequency selected using #pragma
config FPBDIV. The PBCLK divider can be set to divide by 1, 2, 4, or 8.
The following example will set up the Basys MX3 for operation with a SYSCLK frequency of 80 MHz and a PBCLK
frequency of 80 MHz.
#pragma config FNOSC =
#pragma config FSOSCEN =
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Figure 1.4. Remappable output example.
FRCPLL
OFF
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