Sony HCD-LF1 Service Manual page 76

HCD-LF1
• DMB07 BOARD IC801 CXD2753R (DSD DECODER)
Pin No. Pin Name
1 VSCA0
2 XMSLAT
3 MSCK
4 MSDATI
5 VDCA0
6 MSDATO
7 MSREADY
8 XMSDOE
9 XRST
10 SMUTE
11 MCKI
12 VSIOA0
13 EXCKO1
14 EXCKO2
15 LRCK
16 F75HZ
17 VDIOA0
18 to 25 MNT0 to MNT7
26 TCK
27 TDI
28 VSCA1
29 TDO
30 TMS
31 TRST
32 to 34 TEST1 to TEST3
35 VDCA1
36 UBIT
37 XBIT
38 to 41 SUPDT0 to SUPDT3
42 VSIOA1
43, 44 SUPDT4, SUPDT5
45 VDIOA1
46, 47 SUPDT6, SUPDT7
48 SUPEN
49 VSCA2
50 NC
51, 52 TEST4, TEST5
53 NC
54 VDCA2
55 DSADML
56 DSADMR
57 BCKASL
58 VSDSD0
59 BCKAI
60 BCKAO
76
I/O
— Ground terminal (for core)
I Serial data latch pulse signal input from the mechanism controller
I Serial data transfer clock signal input from the mechanism controller
I Serial data input from the mechanism controller
— Power supply terminal (+2.5V) (for core)
O Serial data output to the mechanism controller
O Ready signal output to the mechanism controller
O Serial data output enable signal output terminal
I Reset signal input from the mechanism controller
Soft muting on/off control signal input from the mechanism controller
I
"H": muting on
I Master clock signal (33.8688 MHz) input from the clock generator
— Ground terminal (for I/O)
O Master clock (22.5792 MHz) signal output to the digital audio processor
O External clock signal output terminal
O L/R sampling clock signal (44.1 kHz) output terminal
O Not used
— Power supply terminal (+3.3V) (for I/O)
O Monitor signal output terminal
I Clock signal input terminal (for JTAG)
I Data input terminal (for JTAG)
— Ground terminal (for core)
O Data output terminal (for JTAG)
I Mode selection signal input terminal (for JTAG)
I Reset signal input terminal (for JTAG)
I Input terminal for the test (normally: fixed at "L")
— Power supply terminal (+2.5V) (for core)
O Monitor terminal relative to DST
O Monitor terminal relative to DST
O Supplementary data output terminal
— Ground terminal (for I/O)
O Supplementary data output terminal
— Power supply terminal (+3.3V) (for I/O)
O Supplementary data output terminal
O Supplementary data enable signal output terminal
— Ground terminal (for core)
O Not used
I Input terminal for the test (normally: fixed at "L")
O Not used
— Power supply terminal (+2.5V) (for core)
O DSD data output terminal for L-ch down mix
O DSD data output terminal for R-ch down mix
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for
I
DSD data output "L": input (slave), "H": output (master) Fixed at "L" in this set
— Ground terminal (for DSD data output)
I Clock signal (5.6448 MHz) input terminal
O Bit clock signal (2.8224 MHz) output for DSD data output to the digital audio processor
Description
"L": ready
Not used
"L": reset
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used