Sharp UX-B800A Service Manual page 79

PIN NO.
TQFP QFP
94-95 96-97
107-104, 102-99, 109-106, 104-
76-73, 71-68 101, 78-75, 73-70
30 32
37 39
35 37
36 38
40 42
42 44
38 40
43 45
46 48
29 31
45 47
31 33
32 34
9 11
10 12
7 9
8 10
NAME SYMBOL
nByte Enable nBE0-nBE1
Data Bus D0-D15
Reset RESET
nAddress Strobe nADS
nCycle nCYCLE
Write/nRead W/nR
nVL Bus Access nVLBUS
Local Bus Clock LCLK
Asynchronous ARDY
Ready
nSynchronous nSRDY
Ready
nReady Return nRDYRTN
Interrupt INTR0
nLocal Device nLDEV
nRead Strobe nRD
nWrite Strobe nWR
EEPROM Clock EESK
EEPROM Select EECS
EEPROM Data EEDO
Out
EEPROM Data In EEDI
5 – 9
BUFFER
TYPE
I** Input. Used during LAN91C113 register accesses to
determine the width of the access and the register(s)
being accessed.
I/O24** Bidirectional. 16 bit data bus used to access the
LAN91C113's internal registers. Data bus has weak
internal pullups. Supports direct connection to the
system bus without external buffering.
IS** Input. When this pin is asserted high, the controller
performs an internal system (MAC & PHY) reset. It
programs all the registers to their default value, the
controller will read the EEPROM device through the
EEPROM interface. (Note 5.1) This input is not con-
sidered active unless it is active for at least 100ns to
filter narrow glitches.
IS** Input. For systems that require address latching, the
rising edge of nADS indicates the latching moment
for A1-A15 and AEN. All LAN91C113 internal func-
tions of A1-A15, AEN are latched except for nLDEV
decoding.
I** Input. This active low signal is used to control
LAN91C113 synchronous bus cycles. For write oper-
ation, this signal should be asserted one bus clock
prior to data valid. For read operation, this signal
should be asserted two bus clocks prior to data valid.
IS** Input. Defines the direction of synchronous cycles.
Write cycles when high, read cycles when low.
I with pul- Input. When low, the LAN91C113 synchronous bus
lup** interface is configured for Local Bus mode accesses.
Otherwise, the LAN91C113 is configured for EISA
accesses. Does not affect the asynchronous bus
interface.
I** Input. Used to interface synchronous buses. Maxi-
mum frequency is 50 MHz. This pin should be tied
high if it is in asynchronous mode.
OD16 Open drain output. ARDY may be used when inter-
facing asynchronous buses to extend accesses. Its
rising (access completion) edge is controlled by the
XTAL1 clock and, therefore, asynchronous to the
host CPU or bus clock.
O16 Output. This output is used when interfacing syn-
chronous buses and nVLBUS=0 to extend accesses.
This signal remains normally inactive, and its falling
edge indicates completion. This signal is synchro-
nous to the bus clock LCLK.
I** Input. This input is used to complete synchronous
read cycles.
O24 Interrupt Output - Used to interrupt the Host on a sta-
tus event. Note: The selection bits used to deter-
mined by the value of INT SEL 1-0 bits in the
Configuration Register are no longer required and
have been set to reserved in this revision of the
FEAST family of devices.
O16 Output. This active low output is asserted when AEN
is low and A4-A15 decode to the LAN91C113
address programmed into the high byte of the Base
Address Register. nLDEV is a combinatorial decode
of unlatched address and AEN signals.
IS** Input. Used in asynchronous bus interfaces.
IS** Input. Used in asynchronous bus interfaces.
O4 Output. 4 usec clock used to shift data in and out of
the serial EEPROM.
O4 Output. Serial EEPROM chip select. Used for selec-
tion and command framing of the serial EEPROM.
O4 Output. Connected to the DI input of the serial
EEPROM.
I with pull- Input. Connected to the DO output of the serial
down** EEPROM.
UX-B800A
DESCRIPTION