JVC MX-DVA5 Service Manual page 34

MX-DVA5
SP3721A (RIC1) : DVD Driver
1.Pin layout
1
16
2.Pin Function (1/2)
Symbol
I/O
Pin No.
1 DVDRFP I
2 DVDRFN
3,4 PD1,PD2 I
5~6 A2,B2 I
7~ 8 C2,D2
9 CP I/O
10 CN I/O
11~14 A,B,C,D I
15~16 E,F I
17 CDTE -
18 VCI2 -
19 NC -
20 VNB -
21 DVDPD I
22 DVDLD O
23 CDPD I
24 CDLD O
25 LDON# I
26 VC -
27 VCI -
28 VPB -
29 MIRR O
30 MP -
31 MB -
32 FDCHG# I
33 MLPF -
1-34
64 ~ 49
48
33
17 ~ 32
Function
RF Signal Inputs. Differential RF signal attenuator input pins.
CD Photo detector Interface Inputs. Inputs from the CD photo detector error outputs.
Photo Detector Interface Inputs. AC coupled inputs for the DPD from
the main beam Photo detector matrix outputs.
Differential Phase tracking LPF pin. An external capacitance is
connected between this pin and the CN pin.
Differential Phase tracking LPF pin. An external capacitance is
connected between this pin and the CP pin.
Photo Detector Interface Inputs. Inputs from the main beam Photo
detector matrix outputs.
CD tracking Error Inputs. Inputs from the CD photo detector error outputs.
CD Tracking. E-F Opamp output for feedback.
Reference Voltage input. DC bias voltage input for the servo input reference.
No Connect.
Ground. Ground pin for the servo block.
APC Input. DVD APC input pin from the monitor photo diode.
APC output. DVD APC output pin to control the laser power.
APC Input. DVD APC input pin from the monitor photo diode.
APC output. DVD APC output pin to control the laser power.
APC output. on/off. APC output control pin. A low level activates the
LD output. (open high)
Reference Voltage output. This pin provides the internal DC bias
reference voltage (+2.5+ fix). Output impedance is less than 50 ohms.
Reference Voltage input. DC bias voltage input for the servo input reference.
Power. Power supply pin for the servo block.
Mirror Detect Output. Mirror Detect comparator output. Pseudo CMOS output.
MIRR signal Peak hold pin. An external capacitance is connected to
between this pin and VPB.
MIRR signal Bottom hold pin. An external capacitance is connected to
between this pin and VPB.
Low Impedance Enable. A TTL compatible input pin that activates the FDCHG switches.
A low level activates the switches and the falling edge of the internal FDCHG triggers
the fast decay for the NIRR bottom hold circuit. (open high)
MIRR signal LPF pin. An external capacitance is connected between this pin and VPB.