JVC MX-DVA5 Service Manual page 33

M11B416256A (SIC1) : DRAM
1.Pin layout
V 1 40
CC
I/O0 2 39
I/O1 3 38
I/O2 4 37
I/O3 5 36
V 6 35
CC
I/O4 7 34
I/O5 8 33
I/O6 9 32
I/O7 10 31
N.C 11 30
N.C 12 29
WE 13 28
RAS 14 27
N.C 15 26
A0 16 25
A1 17 24
A2 18 23
A3 19 22
V 20 21
CC
3. Block diagram
WE
CASL
CAS
CASH
No.2 Clock
Generator
Column
9
A0
Address
Buffer
A1
A2
Refresh
A3
Controller
A4
A5
Refresh
Counter
A6
9
A7
A8
Row.
9
Address
Buffers (9)
No.1 Clock
RAS
Generator
2. Pin function
Pin No. Symbol
V
SS
16~19 A0~A3
I/O15
I/O14
22~26 A4~A8
I/O13
2~5 I/O0~3
I/O12
7~10 I/O4~7
V
SS
I/O11
31~34 I/O8~11
I/O10
36~39 I/O12~15
I/O9
I/O8
35,40 Vss
N.C
14 RAS
CASL
28 CASH
CASH
OE
29 CASL
A8
13 WE
A7
A6 27 OE
A5
1,20 Vcc
A4
V
SS
11,12 N.C
Control
Logic
9
9
I/O
I Address Input
I Address Input
I/O Data Input/Output
I/O Data Input/Output
I/O Data Input/Output
I/O Data Input/Output
- Ground
- Row Address Strobe
- Column Address Strobe / Upper Byte Control
-- Column Address Strobe / Lower Byte Control
I Write Enable
O Output Enable
- Power(+5V)
- Power(+3.3V)
- No Connect
DATA-IN Buffer
Data out
Column
Decoder
8
8
512
Sense amplifiers VO gating
512 x 16
512 x 512 x 16
Memory Array
512
512
MX-DVA5
Function
I/O0
16
to
I/O15
Buffer
OE
16
Vcc
Vss
1-33