JVC MX-DVA5 Service Manual page 30

MX-DVA5
KM416C256D (SIC1) : CMOS DRAM
1.Pin layout
V 1
CC
DQ0 2
DQ1 3
DQ2 4
DQ3 5
V 6
CC
DQ4 7
DQ5 8
DQ6 9
DQ7 10
N.C 11
N.C 12
W 13
RAS 14
N.C 15
A0 16
A1 17
A2 18
A3 19
V 20
CC
3. Block diagram
RAS
Control
UCAS
Clocks
LCAS
W
Row Address Buffer
A0~A8
Col. Address Buffer
1-30
2. Pin function
Pin No.
40 V
SS
16~19
39 DQ15
38 DQ14
22~26
37 DQ13
2~5
36 DQ12
7~10
35 V
SS
34 DQ11
31~34
33 DQ10
36~39
32 DQ9
31 DQ8
35,40
14
28
30 N.C
29 LCAS
29
28 UCAS
13
27 OE
26 A8
27
25 A7
1,20
24 A6
23 A5
22 A4
11,12
21 V
SS
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Symbol I/O
A0~A3 I Address Inputs
A4~A8 I Address Inputs
DQ0~3 I/O Data In/Out
DQ4~7 I/O Data In/Out
DQ8~11 I/O Data In/Out
DQ12~15 I/O Data In/Out
Vss - Ground
RAS - Row Address Strobe
UCAS - Upper Column Address Strobe
LCAS -- Lower Column Address Strobe
W I Read/Write Input
OE O Data Output Enable
Vcc - Power(+5V)
- Power(+3.3V)
N.C - No Connection
Vcc
Vss
Row Decoder
Memory Array
262,144 x16
Cells
Column Decoder
Function
Lower
Data in
DQ0
Buffer
to
DQ7
Lower
Data out
Buffer
OE
Upper
Data in
DQ8
Buffer
to
Upper
DQ15
Data out
Buffer