Analog Devices Blackfin Audio EZ-Extender Manual page 17

Daughter board to the ez-kit lite evaluation system for the adsp-bf533, adsp-bf537, and adsp-bf561 blackfin processors.
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• At a 48 kHz sample rate, TDM mode allows up to 16 channels of
data to be sent from each chip in each direction. Each chip uses
four of the 16 input channels and eight of the 16 output channels.
The number of channels can be set up in the control registers and
is dependant on the sample rate. As the sample rate increases, the
number of possible channels decreases.
• At 96 kHz, the AD1938 operates with a maximum of eight chan-
nels in each direction. At 96 kHz, all of the TDM channels are
used by all analog outputs, but there are still four extra input chan-
nels, two of which can be used by the digital inputs.
• At the 192 kHz sample rate, a maximum of four channels in each
direction can be used, meaning that four of the output channels
cannot be used.
The auxiliary SPORTs of the AD1938_A codec connect to the
ADAV801's auxiliary SPORT; see
more information. The Sony Philips Digital Interface (S/PDIF) stream
requires two channels of the TDM stream for each direction: two channels
for left and right input audio, and two channels for left and right output
audio.
If the AD1938 codec runs at the 48 kHz sample rate, both the input and
output digital streams can be put into the TDM stream. In this case, all of
the clocks in the system must be set up relative to the recovered clock from
the SPDIF input.
At the 96 kHz sample rate, only the SPDIF inputs can be added to the
TDM stream. This is because at 96 kHz, only eight outputs channels are
available, and all eight channels are used by the outputs.
The internal phase-locked loop (PLL) of the AD1938 codec can be config-
ured to generate all of the clocking and frame sync signals. The source
clock of the PLL can be from the serial port frame sync or from an exter-
nally supplied clock. The external master clock (
ADAV801 codec. A jumper (
Blackfin Audio EZ-Extender Manual
Blackfin Audio EZ-Extender Interfaces
"System Architecture" on page 2-2
) allows the master clock to come directly
JP2
) comes from the
MCLK
for
1-3

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