HP 54501A Service Manual page 71

Similarly, when power is removed, as the +5 V
supply crosses the lower threshold of the
comparator, the timeout halts the micro-
processor and resets all critical timing before
the +5 V supply falls below the valid operating
region for TTL.
Decoders . The four upper address lines (A23,
A22, A21, and A20) are decoded into function-
al operations for system ROM, non-volatile
static RAM, system RAM, display RAM,
keyboard, HP-IB, CRTC, and an operation cal-
led DEVICES .
The DEVICES operation is further decoded to
clear the RPG and interrupts on the micro-
processor, address the RPG and clic-
ker/beeper, and provide a latch to the data
acquisition .
The address strobe from the microprocessor
and a hardware chip select line from the TCL
provide the functional timing for the address
decoders .
Memory . Memory for the system control of the
HP 54501A is composed of System ROM,
System RAM, and static RAM .
There are 3 Megabits of System ROM con-
figured as two 128K X 8 and one 64K X 16
(256K + 128K) for 384K bytes of CMOS
EPROM with 200 nanoseconds access time.
System ROM is used to store system operating
code, look-up tables, constants, default cal
factors, etc .
The 4 Megabits of System RAM are configured
as four 256K X 4 for 512K bytes of CMOS
dynamic RAM with a 220 , nanosecond cycle
time.
The address inputs to each of the four
RAMs are multiplexed to create an internal ar-
ray of 512 X 512 X 4 . Nine address lines are
used for row decoding and nine are used for
column decoding . The System RAM uses the
conventional RAS/CAS timing scheme for
read/write and refresh . System RAM stores
variables, acquisition data for displaying, and
provides scratch-pad memory for the
microprocessor .
The CMOS static RAM is configured as 32K X
8 with a 120 nanosecond access time. The
static RAM is combined with a smart socket
HP 54501 A SERVICE
that has a built-in controller circuit and an
imbedded lithium energy source . The smart
socket monitors the supply voltage (Vcc) .
When Vcc falls below an acceptable voltage
level, such as during power-down of the HP
54501A, the internal lithium source is auto-
matically switched on and write protection is
unconditionally enabled to prevent garbled
data . The non-volatile static RAM stores menu
configurations, calibration factors, and up to
four waveforms . Normal power-up of the HP
54501A restores the calibration factors as
stored in non-volatile memory and menu con-
figurations from the last power-down state . A
key-down power-up, in which any key is held
down during power-up, does not affect calibra-
tion factors previously stored in non-volatile
memory but resets the HP 54501A menu con-
figurations to known settings .
Interface Circuits . System Control of the HP
54501 A interfaces with four major communica-
tion circuits . These four circuits are the dis-
play monitor, front-panel keypad and RPG,
HP-IB and acquisition .
The display interface consists of a CRT con-
troller IC (CRTC), display RAM, shift registers,
and buffers for address and data lines .
The CRTC provides the horizontal and vertical
sync signals for the CRT and a disable/enable
signal for TCL that is used for generating the
necessary timing for addressing the CRT
screen .
The display RAM is configured in a
row/column matrix . Counters track the
memory location in display RAM versus
positioning the data on the CRT as data is
shifted from display RAM to two shift registers .
The output of the shift registers is two data
streams . One stream is displayed as full-bright
pixel information on the CRT and the other as
half-bright . A character ROM is not utilized in
the display interface because all character
matrices are stored in System ROM .
The HP-IB interface circuitry supports com-
munication with other instruments (printer,
controller, automated test equipment, etc .)
The circuit consists of three main components .
The TMS 9914 GPIB controller provides an
interface between the microprocessor system
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