Digital Specifications - Analog Devices AD9273 Manual

AD9273

DIGITAL SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f
Table 2.
Parameter 1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
2
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, STBY, SCLK)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
3
LOGIC OUTPUT (SDIO)
Logic 1 Voltage (I = 800 μA)
OH
Logic 0 Voltage (I = 50 μA)
OL
DIGITAL OUTPUTS (DOUTx+, DOUTx−) IN ANSI-644 MODE
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
OS
Output Coding (Default)
DIGITAL OUTPUTS (DOUTx+, DOUTx−) WITH
LOW POWER, REDUCED-SIGNAL OPTION
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
OS
Output Coding (Default)
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
1
)
OD
)
1
)
OD
)
= 5 MHz, full temperature, unless otherwise noted.
IN
Temperature Min
Full 250
Full
25°C
25°C
Full 1.2
Full
25°C
25°C
Full 1.2
Full
25°C
25°C
Full 1.2
Full 0
25°C
25°C
Full
Full
Full 247
Full 1.125
Full 150
Full 1.10
Rev. B | Page 8 of 48
Typ Max
CMOS/LVDS/LVPECL
1.2
20
1.5
3.6
0.3
30
0.5
3.6
0.3
70
0.5
DRVDD + 0.3
0.3
30
2
1.79
0.05
LVDS
454
1.375
Offset binary
LVDS
250
1.30
Offset binary
Unit
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V