Adc Timing Diagrams; Changes To Figure 2 And Figure 3 - Analog Devices AD9273 Manual

AD9273

ADC TIMING DIAGRAMS

N – 1
AIN
CLK–
CLK+
DCO–
DCO+
FCO–
FCO+
DOUTx–
DOUTx+
N – 1
AIN
CLK–
CLK+
DCO–
DCO+
FCO–
FCO+
DOUTx–
DOUTx+
t
EH
t
CPD
t
t
FRAME
FCO
t
PD
MSB D10
N – 8 N – 8
Figure 2. 12-Bit Data Serial Stream (Default)
t
EH
t
CPD
t
t
FRAME
FCO
t
PD
D0 D1
(LSB) N – 8
Figure 3. 12-Bit Data Serial Stream, LSB First
t
EL
t
DATA
D9 D8 D7 D6 D5
N – 8 N – 8 N – 8 N – 8 N – 8
t
EL
t
DATA
D2 D3 D4 D5 D6
N – 8 N – 8 N – 8 N – 8 N – 8
Rev. B | Page 10 of 48
N
D4 D3 D2 D1 D0
N – 8 N – 8 N – 8 N – 8 N – 8
N
D7 D8 D9 D10 D11
N – 8 N – 8 N – 8 N – 8 (MSB)
MSB D10
N – 7 N – 7