Analog Devices AD9273 Manual

Octal lna/vga/aaf/adc and crosspoint switch

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User manual (24 pages)

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FEATURES

8 channels of LNA, VGA, AAF, and ADC

Low noise preamplifier (LNA)

Input-referred noise voltage = 1.26 nV/√Hz

(gain = 21.3 dB) @ 5 MHz typical

SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB

Single-ended input; V

maximum = 733 mV p-p/

550 mV p-p/367 mV p-p

Dual-mode active input impedance matching

Bandwidth (BW) > 100 MHz

Full-scale (FS) output = 4.4 V p-p differential

Variable gain amplifier (VGA)

Attenuator range = −42 dB to 0 dB

SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB

Linear-in-dB gain control

Antialiasing filter (AAF)

Programmable 2nd-order low-pass filter (LPF) from

8 MHz to 18 MHz

Programmable high-pass filter (HPF)

Analog-to-digital converter (ADC)

12 bits at 10 MSPS to 50 MSPS

SNR = 70 dB

SFDR = 75 dB

Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)

Data and frame clock outputs

Includes an 8 × 8 differential crosspoint switch to support

continuous wave (CW) Doppler

Low power, 109 mW per channel at 12 bits/40 MSPS (TGC)

70 mW per channel in CW Doppler

Flexible power-down modes

Overload recovery in <10 ns

Fast recovery from low power standby mode, <2 μs

100-lead TQFP and 144-ball BGA

APPLICATIONS

Medical imaging/ultrasound

Automotive radar

GENERAL DESCRIPTION

The AD9273 is designed for low cost, low power, small size, and

ease of use. It contains eight channels of a low noise preamplifier

(LNA) with a variable gain amplifier (VGA); an antialiasing

filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-

digital converter (ADC).

Each channel features a variable gain range of 42 dB, a fully

differential signal path, an active input preamplifier termination, a

maximum gain of up to 52 dB, and an ADC with a conversion

rate of up to 50 MSPS. The channel is optimized for dynamic

performance and low power in applications where a small

package size is critical.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

Octal LNA/VGA/AAF/ADC

and Crosspoint Switch

FUNCTIONAL BLOCK DIAGRAM

LOSW-A

LO-A

LI-A

VGA

LNA

LG-A

LOSW-B

LO-B

LI-B

LNA

VGA

LG-B

LOSW-C

LO-C

LI-C

LNA

VGA

LG-C

LOSW-D

LO-D

LI-D

VGA

LNA

LG-D

LOSW-E

LO-E

LI-E

LNA

VGA

LG-E

LOSW-F

LO-F

LI-F

LNA

VGA

LG-F

LOSW-G

LO-G

LI-G

VGA

LNA

LG-G

LOSW-H

LO-H

LI-H

LNA

VGA

LG-H

SWITCH

ARRAY

The LNA has a single-ended-to-differential gain that is selectable

through the SPI. The LNA input-referred noise voltage is typically

1.26 nV/√Hz at a gain of 21.3 dB, and the combined input-referred

noise voltage of the entire channel is 1.42 nV/√Hz at typical

gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB

LNA gain, the input SNR is about 91 dB. In CW Doppler mode,

the LNA output drives a transconductance amp that is switched

through an 8 × 8 differential crosspoint switch. The switch is

programmable through the SPI.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

AD9273

DOUTA+

12-BIT

SERIAL

ADC

LVDS

DOUTA–

AAF

12-BIT

DOUTB+

SERIAL

ADC

LVDS

DOUTB–

AAF

12-BIT

DOUTC+

SERIAL

ADC

LVDS

DOUTC–

AAF

12-BIT

DOUTD+

SERIAL

ADC

LVDS

DOUTD–

AAF

DOUTE+

12-BIT

SERIAL

ADC

LVDS

DOUTE–

AAF

DOUTF+

12-BIT

SERIAL

ADC

LVDS

DOUTF–

AAF

DOUTG+

12-BIT

SERIAL

ADC

LVDS

DOUTG–

AAF

DOUTH+

12-BIT

SERIAL

ADC

LVDS

DOUTH–

AAF

FCO+

FCO–

REFERENCE

DCO+

DCO–

Figure 1.

www.analog.com

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Summary of Contents for Analog Devices AD9273

Page 1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Page 2: Features
• AD9273 IBIS Models This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
Page 3: Table Of Contents
AD9273 TABLE OF CONTENTS Features ....................1 Theory of Operation ..............21 Applications ..................1 Ultrasound .................. 21 General Description ................. 1 Channel Overview ..............22 Functional Block Diagram .............. 1 Input Overdrive ................25 ...
Page 4: Product Highlights
AD9273 The AD9273 requires a LVPECL-/CMOS-/LVDS-compatible Fabricated in an advanced CMOS process, the AD9273 is sample rate clock for full performance operation. No external available in a 16 mm × 16 mm, RoHS compliant, 100-lead reference or driver components are required for many TQFP or a 144-ball BGA.
Page 5: Specifications
AD9273 SPECIFICATIONS AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f = 5 MHz, R = 50 Ω, LNA gain = 21.3 dB, LNA bias =mid- high (default), PGA gain = 24 dB, GAIN− = 0.8 V, AAF LPF cutoff = f /3 (default), HPF = LPF cutoff/20.7 (default), full temperature,...
Page 6 AD9273 AD9273-25 AD9273-40 AD9273-50 Parameter Conditions Unit AAF Bandwidth In range ±10 ±10 ±10 Tolerance Group Delay f = 1 MHz to ±2 ±2 ±2 Variation 18 MHz, GAIN+ = 0 V to 1.6 V Input-Referred LNA gain = 1.94/1.64/1.38 1.94/1.64/1.38...
Page 7: Changes To Gain Control Interface Parameter And To Cw Doppler Mode Parameter, Table 1
AD9273 AD9273-25 AD9273-40 AD9273-50 Parameter Conditions Unit GAIN ACCURACY 25°C Gain Law Confor- 0 V < GAIN+ mance Error < 0.16 V 0.16 V < GAIN+ −1.6 +1.6 −1.6 +1.6 −1.7 +1.7 < 1.44 V 1.44 V < GAIN+ −2.5 −2.5...
Page 8 AD9273 AD9273-25 AD9273-40 AD9273-50 Parameter Conditions Unit Full-channel AVDD2 mode CW Doppler mode with four channels enabled DRVDD Total Power Includes output 1072 Dissipation drivers, full- channel mode, no signal CW Doppler mode with four channels enabled Power-Down Dissipation Standby Power...
Page 9: Digital Specifications
AD9273 DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f = 5 MHz, full temperature, unless otherwise noted. Table 2. Parameter Temperature Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance...
Page 10: Switching Specifications
AD9273 SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f = 5 MHz, full temperature, unless otherwise noted. Table 3. Parameter Temp Unit CLOCK Clock Rate Full MSPS Clock Pulse Width High (t...
Page 11: Adc Timing Diagrams
AD9273 ADC TIMING DIAGRAMS N – 1 CLK– CLK+ DCO– DCO+ FRAME FCO– FCO+ DATA DOUTx– N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N – 8 N –...
Page 12: Absolute Maximum Ratings
AD9273 ABSOLUTE MAXIMUM RATINGS Table 4. Stresses above those listed under Absolute Maximum Ratings With may cause permanent damage to the device. This is a stress Parameter Respect To Rating rating only; functional operation of the device at these or any...
Page 13: Pin Configuration And Function Descriptions
AD9273 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 LI-E LI-D INDICATOR LG-E LG-D AVDD2 AVDD2 AVDD1 AVDD1 EXPOSED PADDLE, PIN 0 LO-F LO-C (BOTTOM OF PACKAGE) LOSW-F LOSW-C LI-F LI-C AD9273 LG-F LG-C TOP VIEW AVDD2 AVDD2 (Not to Scale)
Page 14: Changes To Table 6
AD9273 Table 6. Pin Function Descriptions Pin No. TQFP Name Description Ground (the exposed paddle should be tied to a quiet analog ground) B5, B6, B8, C5, Ground C6, C7, C8, D5, D6, D7, D8, E1, E5, E6, E7, E8,...
Page 15 AD9273 Pin No. TQFP Name Description DOUTA− ADC A Digital Output Complement DOUTA+ ADC A Digital Output True STBY Standby Power-Down PDWN Full Power-Down SCLK Serial Clock SDIO Serial Data Input/Output Chip Select Bar LG-A LNA Ground for Channel A...
Page 16: Typical Performance Characteristics
AD9273 TYPICAL PERFORMANCE CHARACTERISTICS = 40 MSPS, f = 5 MHz, R = 50 Ω, LNA gain = 21.3 dB, LNA bias = mid-high, PGA gain = 24 dB, AAF LPF cutoff = f SAMPLE SAMPLE HPF = LPF cutoff/20.7 (default), GAIN− = 0.8 V –40°C...
Page 17 AD9273 500k –128 –129 450k –130 400k LNA GAIN = 12× –131 350k –132 300k LNA GAIN = 8× –133 250k –134 200k –135 150k –136 100k –137 LNA GAIN = 6× –138 –139 –7 –6 –5 –4 –3 –2 –1...
Page 18 AD9273 –20 –40 GAIN+ = 1.6V GAIN+ = 0.8V GAIN+ = 0.8V –60 GAIN+ = 0V GAIN+ = 0V GAIN+ = 1.6V –80 –100 –120 –40 –35 –30 –25 –20 –15 –10 –5 ADC OUTPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 18. Antialiasing Filter (AAF) Group Delay Response Figure 21.
Page 19 AD9273 = 5.00MHz, = 5.01MHz FUND2 LEVEL = FUND1 LEVEL – 20dB –20 –40 –60 GAIN+ = 0.8V GAIN+ = 0V –80 –100 GAIN+ = 1.6V –120 –40 –35 –30 –25 –20 –15 –10 –5 FUND1 LEVEL (dBFS) Figure 24. IMD3 vs. Fundamental 1 Amplitude (FUND1) Level...
Page 20: Equivalent Circuits
AD9273 EQUIVALENT CIRCUITS AVDDx AVDDx 15kΩ 350Ω LI-x, SDIO LG-x 30kΩ Figure 25. Equivalent LNA Input Circuit Figure 28. Equivalent SDIO Input Circuit DRVDD AVDDx DOUTx– DOUTx+ 10Ω LO-x, LOSW-x DRGND Figure 26. Equivalent LNA Output Circuit Figure 29. Equivalent Digital Output Circuit 10Ω...
Page 21: Changes To Figure 34 And Figure 35
AD9273 AVDDx 100Ω RBIAS AVDD2 50Ω GAIN+ Figure 31. Equivalent RBIAS Circuit Figure 34. Equivalent GAIN+ Input Circuit AVDDx 70kΩ 1kΩ 0.8V AVDD2 70kΩ 50Ω GAIN– Figure 32. Equivalent CSB Input Circuit Figure 35. Equivalent GAIN− Input Circuit 10Ω CWDx+, +0.5V...
Page 22: Theory Of Operation
TGC amplifier, and then beam forming is ULTRASOUND accomplished digitally. The primary application for the AD9273 is medical ultrasound. The ADC resolution of 12 bits with up to 50 MSPS sampling Figure 37 shows a simplified block diagram of an ultrasound satisfies the requirements of both general-purpose and high- system.
Page 23: Channel Overview
AD9273 LO-x CWD[7:0]+ SWITCH ARRAY CWD[7:0]– LOSW-x SWITCH LI-x DOUTx+ SERIAL ATTENUATOR PIPELINE FILTER POSTAMP LVDS –42dB TO 0dB DOUTx– LG-x 15.6dB, 21dB 17.9dB, 24dB, 21.3dB 27dB, GAIN AD9273 30dB INTERPOLATOR Figure 38. Simplified Block Diagram of a Single Channel...
Page 24: Changes To Active Impedance Matching Section And Figure 40
AD9273 Active Impedance Matching = 500Ω, R = 2kΩ The LNA consists of a single-ended voltage gain amplifier with differential outputs and the negative output available externally. For example, with a fixed gain of 8× (17.9 dB), an active input = 200Ω, R...
Page 25: Changes To Lna Noise Section
AD9273 Figure 42 shows the relative noise figure performance. In this LNA Noise graph, the input impedance was swept with R to preserve the The short-circuit noise voltage (input-referred noise) is an impor- match at each point. The noise figures for a source impedance of tant limit on system performance.
Page 26: Input Overdrive
AD9273 output to provide a differential output of the LNA. The LNA output 10nF full-scale voltage of the AD9273 is 4.4 V p-p, and the input full- scale voltage is 2.7 V p-p. If no attenuation is provided between 2kΩ...
Page 27 AD9273 AD9273 SWITCH ARRAY 8 × CHANNEL AD8333 600µH 2.5V 700Ω 600µH 600µH 2.5V 700Ω 600µH AD8333 AD9273 600µH 700Ω 2.5V 600µH 600µH 2.5V 700Ω 600µH SWITCH ARRAY 8 × CHANNEL 16-BIT 16-BIT Figure 45. Typical Connection Interface with the AD8333 or AD8339 using the CWDx± Outputs 2.5V...
Page 28: Tgc Operation
The system gain is distributed as listed in Table 8. to ensure that the full-scale swing and common-mode voltage Table 8. Channel Gain Distribution are within the operating limits of the AD9273. When interfacing Section Nominal Gain (dB) to the AD8339, a common-mode voltage of 2.5 V and a full-scale 15.6/17.9/21.3...
Page 29: Changes To Figure 48
AD9273 1, 2, 3 Table 9. Sensitivity and Dynamic Range of Trade-Offs Channel Gain Typical Output Dynamic Range Input-Referred Full-Scale Input Noise Voltage Input-Referred Noise (V/V) (dB) (V p-p) (nV/√Hz) Postamp Gain (dB) GAIN+ = 0 V GAIN+ = 1.6 V GAIN+ = 1.6 V (nV/√Hz)
Page 30: Changes To Figure 49 And Figure 50
AD9273 per side is 180 Ω nominally for a total differential resistance of PGA GAIN = 21dB 360 Ω. The ladder is driven by a fully differential input signal from the LNA. LNA outputs are dc-coupled to avoid external decoupling capacitors.
Page 31 AD9273 499Ω The antialaising filter is a combination of a single-pole high- AVDD2 pass filter and a second-order low-pass filter. The high-pass AD9273 ±0.4VDC AT 31.3kΩ 499Ω 100Ω 0.8V CM filter can be configured at a ratio of the low-pass filter cutoff.
Page 32: Adc
0.1µF 39kΩ through to other portions of the AD9273, and it preserves the fast rise and fall times of the signal, which are critical to low 50Ω RESISTOR IS OPTIONAL.
Page 33 MID-HIGH Figure 60. Ideal SNR vs. Analog Input Frequency and Jitter Power Dissipation and Power-Down Mode As shown in Figure 62, the power dissipated by the AD9273 is MID-LOW proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers.
Page 34: Changes To Digital Outputs And Timing Section
No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended By asserting the STBY pin high, the AD9273 is placed into a that the trace length be no longer than 24 inches and that the standby mode.
Page 35 AD9273 EYE: ALL BITS EYE: ALL BITS ULS: 2398/2398 ULS: 2399/2399 –100 –100 –200 –200 –400 –300 –600 –400 –1.5ns –1.0ns –0.5ns 0.5ns 1.0ns 1.5ns –1.5ns –1.0ns –0.5ns 0.5ns 1.0ns 1.5ns –200ps –100ps 100ps 200ps –200ps –100ps 100ps 200ps Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Figure 66.
Page 36 Two output clocks are provided to assist in capturing data from the AD9273. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the AD9273 and must be captured on the rising and falling edges of the DCO±...
Page 37: Changes To Csb Pin Section
A stable and accurate 0.5 V voltage reference is built into the except PN sequence short and PN sequence long can support AD9273. This is gained up internally by a factor of 2, setting 8- to 14-bit word lengths in order to verify data capture to the VREF to 1.0 V, which results in a full-scale differential input...
Page 38 AD9273 Power and Ground Recommendations the AD9273 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal When connecting power to the AD9273, it is recommended path for heat dissipation to flow through the bottom of the PCB.
Page 39: Serial Port Interface (Spi)
Figure 70 and Table 16. Figure 69 shows the number of SDIO pins that can be connected together, assuming the same load as the AD9273, as well as the During normal operation, CSB is used to signal to the device resulting V level.
Page 40 AD9273 This interface is flexible enough to be controlled by either serial If the user chooses not to use the SPI interface, these pins serve PROMS or PIC mirocontrollers. This provides the user with a dual function and are associated with secondary functions an alternative method, other than a full SPI controller, for when the CSB is strapped to AVDD during device power-up.
Page 41: Memory Map
AD9273 MEMORY MAP RESERVED LOCATIONS READING THE MEMORY MAP TABLE Undefined memory locations should not be written to except Each row in the memory map table has eight address locations. when writing the default values suggested in this data sheet.
Page 42 AD9273 Table 17. AD9273 Memory Map Register Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments Chip Configuration Registers CHIP_PORT_CONFIG LSB first...
Page 43 AD9273 Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments FLEX_CHANNEL_ Filter cutoff frequency control 0x30 Antialiasing filter INPUT 0000 = 1.3 × 1/3 × f cutoff (global).
Page 44 AD9273 Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments USER_PATT1_LSB 0x00 User-defined pattern, 1 LSB (global). USER_PATT1_MSB 0x00 User-defined pattern, 1 MSB (global).
Page 45: Outline Dimensions
AD9273 OUTLINE DIMENSIONS 16.00 BSC SQ 1.20 0.75 0.60 14.00 BSC SQ 0.45 PIN 1 EXPOSED 9.50 SQ TOP VIEW (PINS DOWN) 0° MIN 1.05 0.20 BOTTOM VIEW 1.00 0.09 (PINS UP) 0.95 7° 3.5° 0.50 BSC 0.27 VIEW A 0.15...
Page 46: Ordering Guide
AD9273 ORDERING GUIDE Temperature Package Model Range Package Description Option AD9273BSVZ-50 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3 AD9273BSVZRL-50 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3 AD9273BSVZ-40 −40°C to +85°C...
Page 47 AD9273 NOTES Rev. B | Page 46 of 48...
Page 48 AD9273 NOTES Rev. B | Page 47 of 48...

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