Analog Devices AD9273 Manual page 42

Table 17. AD9273 Memory Map Register
Addr. Bit 7
(Hex) Register Name (MSB)
Chip Configuration Registers
00 CHIP_PORT_CONFIG 0
01 CHIP_ID
02 CHIP_GRADE X
Device Index and Transfer Registers
04 DEVICE_INDEX_2 X
05 DEVICE_INDEX_1 X
FF DEVICE_UPDATE X
ADC Functions Registers
08 Modes X
09 Clock X
0D TEST_IO User test mode
00 = off (default)
01 = on, single
alternate
10 = on, single once
11 = on, alternate once
Bit 6 Bit 5 Bit 4
LSB first Soft 1
1 = on reset
0 = off 1 = on
(default) 0 = off
(default)
Chip ID Bits[7:0]
(AD9273 = 0x2F, default)
X Child ID[5:4]
(identify device
variants of Chip ID)
00 = 40 MSPS
(default)
01 = 25 MSPS
10 = 50 MSPS
X X X
X Clock Clock
Channel Channel
DCO± FCO±
1 = on 1 = on
0 = off 0 = off
(default) (default)
X X X
X X X
X X X
Reset PN
Reset PN
long short
gen gen
1 = on 1 = on
0 = off 0 = off
(default) (default)
Rev. B | Page 41 of 48
Bit 3 Bit 2 Bit 1
1 Soft LSB first
reset 1 = on
1 = on 0 = off
0 = off (default)
(default)
X X X
Data Data Data
Channel Channel Channel
H G F
1 = on 1 = on 1 = on
(default) (default) (default)
0 = off 0 = off 0 = off
Data Data Data
Channel Channel Channel
D C B
1 = on 1 = on 1 = on
(default) (default) (default)
0 = off 0 = off 0 = off
X X X
0 Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
100 = CW mode (TGC PDWN)
X X X
Output test mode—see Table 12
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by the OUTPUT_MODE register)
AD9273
Bit 0 Default Default Notes/
(LSB) Value Comments
0 0x18 The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless
of shift mode.
Read Default is unique
only chip ID, different
for each device.
This is a read-only
register.
X 0x00 Child ID used to
differentiate
graded devices.
Data 0x0F Bits are set to
Channel determine which
E on-chip device
1 = on receives the next
(default) write command.
0 = off
Data 0x0F Bits are set to
Channel determine which
A on-chip device
1 = on receives the next
(default) write command.
0 = off
SW 0x00 Synchronously
transfer transfers data
1 = on from the master
0 = off shift register to
(default) the slave.
0x00 Determines
various generic
modes of chip
operation
(global).
Duty 0x01 Turns the internal
cycle duty cycle stabilizer
stabilizer on and off
(global).
1 = on
(default)
0 = off
0x00 When this register
is set, the test data
is placed on the
output pins in
place of normal
data. (Local, expect
for PN sequence.)