Analog Devices AD9273 Manual page 43

AD9273
Addr.
(Hex) Register Name
0F FLEX_CHANNEL_
INPUT
10 FLEX_OFFSET
11 FLEX_GAIN
12 BIAS_CURRENT
14 OUTPUT_MODE
15 OUTPUT_ADJUST
16 OUTPUT_PHASE
18 FLEX_VREF
Bit 7
(MSB) Bit 6 Bit 5
Filter cutoff frequency control
0000 = 1.3 × 1/3 × f
SAMPLE
0001 = 1.2 × 1/3 × f
SAMPLE
0010 = 1.1 × 1/3 × f
SAMPLE
0011 = 1.0 × 1/3 × f (default)
SAMPLE
0100 = 0.9 × 1/3 × f
SAMPLE
0101 = 0.8 × 1/3 × f
SAMPLE
0110 = 0.7 × 1/3 × f
SAMPLE
1000 = 1.3 × 1/4.5 × f
SAMPLE
1001 = 1.2 × 1/4.5 × f
SAMPLE
1010 = 1.1 × 1/4.5 × f
SAMPLE
1011 = 1.0 × 1/4.5 × f
SAMPLE
1100 = 0.9 × 1/4.5 × f
SAMPLE
1101 = 0.8 × 1/4.5 × f
SAMPLE
1110 = 0.7 × 1/4.5 × f
SAMPLE
X X 6-bit LNA offset adjustment
10 0000 = LNA bias high, mid-high, mid-low (default)
10 0001 = LNA bias low
X X X
X X X
X 0 = LVDS X
ANSI-644
(default)
1 = LVDS
low power,
(IEEE
1596.3
similar)
X X Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X X X
X 0 = X
internal
reference
1 =
external
reference
Bit 4 Bit 3 Bit 2
X X
X PGA gain
00 = 21 dB
01 = 24 dB (default)
10 = 27 dB
11 = 30 dB
X 1 X
X X Output
invert
1 = on
0 = off
(default)
X X
X 0011 = output clock phase adjust
(0000 through 1010)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge (default)
0100 = 240° relative to data edge
0101 = 300° relative to data edge
0110 = 360° relative to data edge
0111 = 420° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
X X X
Rev. B | Page 42 of 48
Bit 0 Default
Bit 1 (LSB) Value
X X 0x30
0x20
LNA gain 0x06
00 = 15.6 dB
01 = 17.9 dB
10 = 21.3 dB
(default)
LNA bias 0x08
00 = high
01 = mid-high
(default)
10 = mid-low
11 = low
00 = offset binary 0x00
(default)
01 = twos
complement
X DCO± 0x00
and
FCO±
2× drive
strength
1 = on
0 = off
(default)
0x03
X X 0x00
Default Notes/
Comments
Antialiasing filter
cutoff (global).
LNA force offset
correction
(local).
LNA and PGA
gain adjustment
(global).
LNA bias current
adjustment
(global).
Configures the
outputs and the
format of the data
(Bits[7:3] and
Bits[1:0] are global;
Bit 2 is local).
Determines LVDS
or other output
properties. Pri-
marily functions to
set the LVDS span
and common-
mode levels in
place of an
external resistor
(Bits[7:1] are global;
Bit 0 is local).
On devices that
utilize global
clock divide,
determines which
phase of the
divider output is
used to supply
the output clock.
Internal latching
is unaffected.
Select internal
reference
(recommended
default) or external
reference (global).