Sony BVP-900P Maintenance Manual page 157

AM29F040B-90JC (AMD)
C-MOS 4 M (524,288 x 8)-BIT FLASH MEMORY
—TOP VIEW—
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
PIN PIN
I/O SIGNAL I/O SIGNAL
No. No.
1 I A18 17 I/O DQ3
2 I A16 18 I/O DQ4
3 I A15 19 I/O DQ5
4 I A12 20 I/O DQ6
5 I A7 21 I/O DQ7
CE
6 I A6 22 I
7 I A5 23 I A10
OE
8 I A4 24 I
9 I A3 25 I A11
10 I A2 26 I
A9
11 I A1 27 I A8
12 I A0 28 I A13
13 I/O DQ0 29 I A14
14 I/O DQ1 30 I A17
WE
15 I/O DQ2 31 I
16 — GND 32 — V
DD
MSM514252A-80JSR1
TC524256BJ-10-EL (TOSHIBA)CHIP CARRIER
C-MOS 1M (262,144 WORD x 4)-BIT MULTIPORT DRAM
—TOP VIEW—
SC 1 GND 28
IN
SIO1 2 27 SIO4
I/O I/O
SIO2 3 26 SIO3
I/O I/O
DT OE SE
/ 4 25
IN IN
W1/IO1 5 24 W4/IO4
I/O I/O
W2/IO2 6 23 W3/IO3
I/O I/O
WB WE
/ 7 NC 22
IN
CAS
8 NC 21
IN
RAS
9 NC 20
IN
A8 10 19 A0
IN IN
A6 11 18 A1
IN IN
A5 12 17 A2
IN IN
A4 A3
13 16
IN IN
14 V 15 A7
CC IN
BVP-900
BVP-900P
12
A0
11
A1
10
A2
9
A3
8
A4
7
A5
6
A6
5 13
A7 DQ0
27 14
A8 DQ1
26 15
A9 DQ2
23 17
A10 DQ3
25 18
A11 DQ4
4 19
A12 DQ5
28 20
A13 DQ6
29 21
A14 DQ7
3
A15
2
A16
30
A17
1
A18
22
CE
24
OE
31
WE
INPUT
A0 - A18 : ADDRESS INPUTS
CE
: CHIP ENABLE
OE
: OUTPUT ENABLE
WE
: WRITE ENABLE
INPUT/OUTPUT
DQ0 - DQ7 : DATA INPUT/OUTPUT
INPUT
A0 - A8 : ADDRESS
CAS
: COLUMN ADDRESS STROBE
DT OE
/ : DATA TRANSFER/OUTPUT ENABLE
RAS
: ROW ADDRESS STROBE
SC : SERIAL CLOCK
SE
: SERIAL ENABLE
WB WE
/ : WRITE PER BIT/WRITE ENABLE
INPUT/OUTPUT
SIO1 - SIO4 : SERIAL DATA
W1/IO1 - W4/IO4 : WRITE MASK/DATA
CXD8889R (SONY)
C-MOS SERIAL I/O
—TOP VIEW—
49
50
51
52
53
54
55
56
57 V
DD
58 GND
59
60
61
62 NC
GND
63 V
DD
64
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO. NO.
1 I/O D0 17 — IC 33
2 I/O D1 18 — IC 34
3 I/O D2 19 — IC 35
4 I/O D3 20 — NC 36
5 I/O D4 21 O BCKO 37
6 I/O D5 22 O IVH 38
7 I/O D6 23 O TVD 39
8 I/O D7 24 — GND 40
9 — GND 25 — V 41
DD
10 — V 26 — IC 42
DD
11 — IC 27 — IC 43
12 — IC 28 — IC 44
13 — IC 29 — IC 45
14 — IC 30 — IC 46
15 — IC 31 — IC 47
16 — IC 32 — IC 48
IC : INTERNAL CONNECTION (NO CONNECTION)
INPUT
A0 - A2 : ADDRESS
BRDI : BI-PHASE RECEIVE DATA
CLK : CLOCK
CS
: CHIP SELECT
RD
: READ ENABLE
RESE : RESET
RVD : SERIAL DATA
SEL : CPU INTERFACE TIMING SELECT
WR
: WRITE ENABLE
OUTPUT
BCKO : INTERNAL CLOCK
BRDO : DEMODULATED BI-PHASE RECEIVE DATA
BTVD : MODULATED BI-PHASE TRANSMISSION DATA
IVH : RECEIVE DATA INTERRUPT
TVD : SERIAL DATA
INPUT/OUTPUT
D0 - D7 : PARALLEL DATA
32
31
30
29
28
27
26
V 25
DD
GND 24
23
22
21
NC 20
19
18
17
PIN
I/O SIGNAL I/O SIGNAL
NO.
— IC 49 — IC
— IC 50 — IC
— IC 51 — IC
— IC 52 — IC
I SEL 53 — IC
I RVD 54 — IC
I RESE 55 — IC
WR
I 56 — IC
— GND 57 — V
DD
— V 58 — GND
DD
RD
I 59 I BRDI
CS
I 60 O BRD0
I CLK 61 O BTVD
I A2 62 — NC
I A1 63 — V
DD
I A0 64 — GND
2-31
IC