Sony BVP-900P Maintenance Manual page 139

HM53461JP-12 (HITACHI)CHIP CARRIER(ACCESS TIME=120 ns)
C-MOS 64K WORD x 4 BIT MULTI PORT RAM
—TOP VIEW—
PIN
I/O
1 GND 24
No.
23
2
1 —
22
3
2 I/O
21
4
3 I/O
20
5
4 —
6 19
5 I/O
18
7
6 I/O
17
8
7 —
16
9
8 —
10 15
9 I
11 14
10 I
12 V 13
CC(+5V)
11 I
12 —
A0 - A7
17 5
A0 I/O1
CAS
16 6
A1 I/O2
DT/OE
15 19
A2 I/O3
I/O1 - I/O4
14 20
A3 I/O4
RAS
11 2
A4 SI/O1
SC
10 3
A5 SI/O2
SI/O1 - SI/O4
9 22
A6 SI/O3
SOE
13 23
A7 SI/O4
WE
8
RAS
18
CAS
7
WE
4
DT/OE
21
SOE
1
I/O1
5
WRITE MASK
GENERATOR
7 WE CLOCK
WE
GENERATOR
18 CAS CLOCK
CAS
GENERATOR
8
RAS CLOCK
RAS
GENERATOR
256 x 4 DATA
13 - 17, 9 - 11
A0 - A7
X ADDRESS
BUFFER
Y ADDRESS
BUFFER
REFRESH ADDRESS
COUNTER
8 18
2
RAS CAS
SI/O1
BVP-900
BVP-900P
PIN
SIGNAL I/O SIGNAL
No.
SC 13 I A7
SI/O1 14 I A3
SI/O2 15 I A2
DT/OE 16 I A1
I/O1 17 I A0
I/O2 18 — CAS
WE 19 I/O I/O3
RAS 20 I/O I/O4
A6 21 — SOE
A5 22 I/O SI/O3
A4 23 I/O SI/O4
V 24 — GND
CC
; ADDRESS INPUT
; COLUMN ADDRESS STROBE INPUT
; DATA TRANSMISSION/OUTPUT ENABLE INPUT
; RAM PORT DATA INPUT/OUTPUT
; ROW ADDRESS STROBE INPUT
; SERIAL CLOCK INPUT
; SAM PORT DATA INPUT/OUTPUT
; SAM PORT ENABLE INPUT/OUTPUT
; WRITE ENABLE INPUT
I/O2 I/O3 I/O4
6 19 20
OE CLOCK
I/O BUFFER
GENERATOR
4
DT/OE
TRANSFER
Y DECODER
CONTROL
64K x 4
MEMORY
SOE CLOCK 21
SOE
ARRAY
GENERATOR
SC CLOCK 1
SC
GENERATOR
REGISTER
POINTER
VBB
SI/O BUFFER
GENERATOR
3 22 23
SI/O2 SI/O3 SI/O4
HM62V256LT8Z (HITACHI)
C-MOS SRAM
—TOP VIEW—
OE 1
IN
A11 2
IN
3 NC
A9 4
IN
A8 5
IN
A13 6
IN
WE 7
IN
8 V
DD ( +3V )
A14 9
IN
A12 10
IN
A7 11
IN
A6 12
IN
A5 13
IN
14 NC
A4 15
IN
A3 16
IN
A0 - A14 ; ADDRESS INPUTS
20 21
A0
I/O0
CS
18 22 ; CHIP SELECT INPUT
A1 I/O1
17 23
I/O0 - I/O7 ; DATA INPUTS/OUTPUTS
A2 I/O2
16 25
OE
; OUTPUT ENABLE INPUT
A3 I/O3
15 26
WE
A4 I/O4
; WRITE ENABLE INPUT
13 27
A5 I/O5
12 28
A6 I/O6
11 29
A7 I/O7
5
CS OE WE MODE
A8
4
1 X X
NO SELECTION
A9
32
A10
0 1 1 OUTPUT DISABLE
2
A11
0 0 1 READ
10
A12
6 0 1 0 WRITE
A13
9
0 0 0 WRITE
A14
0 ; LOW LEVEL
31
CS
1 ; HIGH LEVEL
1
OE X
; DON'T CARE
7
WE
HI-Z ; HIGH IMPEDANCE
10
( MSB ) A12
13
A5
11
A7
12
A6
ROW
5
A8
DECODER
6
A13
9
A14
15
A4
16
( LSB ) A3
21 - 23,
25 - 29
I/O0
INPUT
DATA
CONTROL
29
I/O7
( LSB )
31
TIMING PULSE GENERATOR
CS
7
WE READ/WRITE CONTROL
1
OE
32 A10
IN
31 CS
IN
NC 30
29 I/O7
I/O
28 I/O6
I/O
27 I/O5
I/O
26 I/O4
I/O
25 I/O3
I/O
GND 24
23 I/O2
I/O
22 I/O1
I/O
21 I/O0
I/O
20 A0
IN
NC 19
18 A1
IN
17 A2
IN
I/O PIN
HI-Z
HI-Z
D
OUT
D
IN
D
IN
MEMORY MATRIX
512 x 512
COLUMN I/O
COLUMN DECODER
A2 A1 A0 A10 A9 A11
( MSB )
2-13
IC