Sony BVP-900P Maintenance Manual page 147

MC14015BF (MOTOROLA)FLAT PACKAGE
MC14015BFEL
C-MOS DUAL 4-STAGE STATIC SHIFT REGISTER WITH DIRECT RESET
—TOP VIEW—
V
DD
CK2 1 16
( CLOCK )
( +3 to +18V )
D2 + 4
2 15 D2
D1 + 3
3 14 RD2
D1 + 2 4 13 D2 +1
D1 + 1
5 12 D2 +2
RD1 6 11 D2 +3
D1 7 10 D1 +4
8 GND 9 CK1 ( CLOCK )
D1 +1 D1 +2
5 4
7
D1 D Q D Q D
Q Q
R R
D D
9
CK1
6
R 1
D
15
D2 D Q D Q D
Q Q
R R
D D
1
CK2
14
R 2
D
13 12
D2 +1 D2 +2
MC14020BFEL (MOTOROLA)FLAT PACKAGE
C-MOS 14-STAG RIPPLE-CARRY BINARY COUNTER/DRIVER
—TOP VIEW—
*
Q11 1 V 16
OUT
DD
Q12 OUT 2 15 Q10
OUT
Q13 OUT 3 14 Q9
OUT
Q5 4 13 Q7
OUT
OUT
Q4 OUT 5 12 Q8
OUT
Q6 OUT 6 11 R
D IN
Q3 7 10 CK
OUT IN
8 GND 9
Q0
OUT
BINARY OUTPUTS
COUNT
Q13 Q12 Q11 Q10 Q9 Q8 Q7
0 0000 0 0 0 0 0 0 0
1 0001 0 0 0 0 0 0 0
2 0002 0 0 0 0 0 0 0
3 0003 0 0 0 0 0 0 0
4 0004 0 0 0 0 0 0 0
16380 4FFC 1 1 1 1 1 1 1
16381 4FFD 1 1 1 1 1 1 1
16382 4FFE 1 1 1 1 1 1 1
16383 4FFF 1 1 1 1 1 1 1
IN HEXADECIMAL
IN DECIMAL
Q0
H 9 H H H
J Q J Q J Q J
10
CK
K R K R K R K R
D D D
H H H H
11
R
D
BVP-900
BVP-900P
5
D+1
7 4
D D+2
9 3
D+3
10
D+4
R
D
6
13
D+1
15 12
D D+2
1 11
D+3
2
D+4
R
D
14
D1 +3
3
Q D Q
10
Q Q D1 +4
R R
D D
Q D Q
2
Q Q D2 +4
R R
D D
11
D2 +3
9
Q0
7
Q3
5
Q4
4
Q5
6
Q6
13
Q7
12
10
Q8
14
Q9
15
Q10
1
Q11
2
Q12
3
Q13
R
D
11
*
TYPE V
DD
+2 to +6V
HC4020
14020, 4020, 84020 +3 to +18V
Q6 Q5 Q4 Q3 Q0
0 0 0 0 0
0 0 0 0 1
0 0 0 0 0
0 0 0 0 1
0 0 0 0 0
1 1 1 1 0
Q13-Q0
RD
1 1 1 1 1
ALL LOW
1
1 1 1 1 0
0 COUNT
1 1 1 1 1
0 ; LOW LEVEL
1 ; HIGH LEVEL
Q3 Q12
7 H 2 H
3
Q J Q J Q Q13
K K R
D D
H H
MC14046BF (MOTOROLA)FLAT PACKAGE
MC14046BF-T2
C-MOS PHASE LOCKED LOOP
—TOP VIEW—
PCP ( PHASE COMPARATOR ) OUT 1
PC 2
1 ( PHASE COMPARATOR ) OUT
PC B ( PHASE COMPARATOR ) IN 3
VCO ( VOLTAGE CONTROLLED OSC ) OUT 4
INH 5
( INHIBIT ) IN
C1
A
6
C1
B
7
8 GND
PHASE 2
SELF
14
COMPARATOR 1
PCA BIAS
CIRCUIT
13
PHASE
3 1
COMPARATOR 2
PCB
4
9
11
VCO
12
VCO
6
7
SOURCE
10
5
FOLLOWER
INH
15
GND
*1
TYPE V
DD
CD4046BE
HD14046BP
MC14046BCP +3 to +8V
MC14046BF
TC4046BP
CD74HC4046AM
+2 to +6V
MC74HC4046AF
MC74HC4046AN
MN6790S (MATSUSHITA)
C-MOS CLOCK GENERATOR
—TOP VIEW—
1 D-GND 14 VCO1
IN
A-V
DD
PC 2 13
OUT
(+4.5 to +5.5 V)
D-V
DD
3 A-GND 12
(+4.5 to +5.5 V)
PC1 4 11 TEST2
IN OUT
PC2 5 10 TEST1
IN IN
DIV 6 9 MOD1
OUT IN
MOD2 7 8 CK
IN OUT
PC VCO1
2 14
4
PHASE
PC1 11
VCO
5
COMPARATOR
PC2
1/2
1/684,
6
1/858,
DIV
1/864
8
CK
FREQUENCY
MOD1 MOD2 VCO NOTE
RATIO
1/684
0 0
1/858
1 0 OSCILLATION
0 1 1/864
1 1 — STANDSTILL CK=DIV=L
0 : LOW LEVEL
1 : HIGH LEVEL
*
1
V 16
DD
15 Z
D ( ZENER ) OUT
14 PC A ( PHASE COMPARATOR ) IN
13 PC 2 ( PHASE COMPARATOR ) OUT
R
2
12
R
1
11
10 SF ( SOURCE FOLLOWER ) OUT
9 VCO ( VOLTAGE CONTROLLED OSC ) IN
14 2
PC1
PCA PC1
13
PC2
3 1
PCB PCP
PC2
PCP 9 4
VCO VCO
IN OUT
11 6
R1 C1A
VCO
12 7
R2 C1B
R1
10
R2 SF
5 15
C1A
INH ZD
C1B
SF
ZD
4 2
PC1 PC
5
PC2
14 11
VCO1 TEST2
6
DIV
8
TEST2
—
2-21
IC