Sony BVP-900P Maintenance Manual page 148

IC
MN8232A (MATSUSHITA)
PICTURE IN PICTURE/PICTURE OUT PICTURE CONTROLLER
—TOP VIEW—
1
GND
2 GND
3
4
5
6
7
8 V DD ( +5 V )
9
10
11 V DD ( +5 V )
12
13
14
15
16
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
1 — GND 17 O
2 — GND 18 O
3 — VRB 19 —
4 I TEST0 20 I
5 I Y 21 I
6 I RY 22 O
7 I BY 23 I
8 — V 24 I
DD
9 — VRT 25 I
10 I TEST1 26 I
11 — V 27 O
DD
12 I IREF 28 I
13 I VREF 29 —
14 O Y 30 I IREFVC
15 I COMP 31 —
16 I VIB 32 O
9
VRT
5
Y
AD
6
7
RY
CONVERTER VERTICAL
7
BY
FILTER
3
VRB
13
+
VREF ELECTRIC
12
_
IREF CURRENT
15
COMP
16
VIB
DA
14
7
CONVERTER
Y
DA
17
6
CONVERTER
RY
DA
18
6
CONVERTER
BY
2-22
48
47
46
45
44
43
42
41
40
39
GND 38
V 37
DD ( +5 V )
36
35
34
33
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
RY 33 O YS 49 O RAS
BY 34 I HP 50 O WE
GND 35 O PPC 51 O DT
RST 36 I PVC 52 O SC
SCL 37 — V 53 I LEV1
DD
SDA 38 — GND 54 I LEV0
VPD 39 O A0 55 I DI3
VCD 40 O A1 56 — V
DD
CKCNT 41 O A2 57 — GND
CVC 42 O A3 58 I DI2
CPC 43 O A4 59 I DI1
HC 44 O A5 60 I DI0
GND 45 O A6 61 O DO3
46 O A7 62 O DO2
V 47 O A8 63 O DO1
DD
CLAMP 48 O CAS 64 O DO0
MULTIPLEXER
STORE READ
BUFFER BUFFER
MEMORY MEMORY
DEMULTIPLEXER
FRAME
COMPOSITE
FRAME COLOR
LEVEL
STORE READ
CONTROL CONTROL
SAMPLING
2
I C
CLOCK
CONTROL
GENERATOR GENERATOR
MSM82C51A-2GS-K (OKI)FLAT PACKAGE
C-MOS PROGRAMMABLE COMMUNICATION INTERFACE
—TOP VIEW—
D2 1
I/O
D3 2
I/O
RXD 3 V
IN
4 NC
5 GND
D4 6
I/O
D5 7
I/O
D6 8
I/O
D7 9
I/O
TXC
10
IN
WR
11
IN
CS
12
IN
13 NC
D
C/ 14
IN
RD
15
IN
RXRDY 16
OUT
OPERATION WITH CPU
CS D RD WR
C/
x x x
1
x
0 1 1
0 1 0 1
0 1 1 0 CONTROL WORD FROM CPU
0 0 0 1
0 0 1 0
INPUT
CK : CLOCK SIGNAL
CS : CHIP ENABLE
CTS : CLEAR TO SEND DATA
D
C/ : DATA, COMMAND WORD OR STATUS WORD
52 IS TO BE WRITTEN OR READ
SC
51
DSR : DATA SET READY
DT
50
RD : READ DATA OR STATUS WORD
WE
49
RESET : RESET BY HIGH LEVEL
RAS
48
CAS RXC : RECEIVING CLOCK
47
A8
RXD : RECEIVING DATA
46
A7
TXC : TRANSMITTING CLOCK
45
A6
WR : WRITE DATA OR CONTROL WORD
44
A5
43
A4
42 OUTPUT
A3
41
DTR : DATA TERMINAL READY
A2
40
RTS : REQUEST TO SEND DATA
A1
39
RXRDY : RECEIVING READY
A0
TXD : TRANSMITTING DATA
TXEMPTY : TRANSMITTING CHARACTER EMPTY
TXRDY : TRANSMITTING READY
DISPLAY
CLOCK
INPUT/OUTPUT
D0 - D7 : DATA
SYNDET/BD : SYNC DETECT/BREAK DETECT
31, 32, 1, 2,
6, 7, 8, 9
DATA
D7 - D0 BUS
BUFFER
24
RESET
23
READ/
CK
14
WRITE
D
C/
CONTROL
15
RD
LOGIC
11
WR
12
CS
25
DSR
27
DTR MODEM
19
CONTROL
CTS
26
RTS
D0
32 D1
I/O
D1
23
CK D2
31 D0
I/O 14
D
C/ D3
15
RD D4
30
DD (+5 V)
11
WR D5
12
CS D6
NC 29
24
RESET D7
RXC
28
IN 25
DSR TXD
27
DTR TXRDY
DTR
27
OUT
19
CTS TXEMPTY
26
RTS TXC
RTS
26
OUT
RXD
DSR
25
IN
RXRDY
RXC
24 RESET
IN
SYNDET/BD
23 CK
IN
22 TXD
OUT
21 TXEMPTY
OUT
NC 20
CTS
19
IN
18 SYNDET/BD
I/O
17 TXRDY
OUT
FUNCTION
DATA BUS 3-STATE
DATA BUS 3-STATE
STATUS TO CPU
0 : LOW LEVEL
1 : HIGH LEVEL
DATA TO CPU
x : DON'T CARE
DATA FROM CPU
HI-Z : HIGH IMPEDANCE
TRANSMIT
22
BUFFER TXD
(P-S)
17
TXRDY
TRANSMIT 21
TXEMPTY
CONTROL
10
TXC
RECEIVE
3
RXD
BUFFER
(S-P)
16
RXRDY
RECEIVE 28
RXC
INTERNAL
CONTROL
18
DATA BUS
SYNDET/BD
31
32
1
2
6
7
8
9
22
17
21
10
3
16
28
18
BVP-900
BVP-900P