Sony BVP-900P Maintenance Manual page 154

IC
TC7W02F (TOSHIBA)FLAT PACKAGE
TC7W02FU(TE12R)
C-MOS DUAL 2-INPUT NOR GATE
—TOP VIEW—
(+2 to +6V)
1A 1 8
V
DD
1B 2 7 1Y
2Y 3 6 2B
4 2A
GND 5
TC7W04FU(TE12R) (TOSHIBA)FLAT PACKAGE
C-MOS HEX INVERTERS
—TOP VIEW—
1 8 V
DD(+2 to +6V)
2 7
3
6
GND 4 5
TC7W08FU (TOSHIBA)CHIP PACKAGE
TC7W08FU(TE12R)
C-MOS 2-INPUT AND GATE
(SCALE 3/1)
—TOP VIEW—
1
8 V
DD(+2 to +6V)
2 7
3 6
GND 4 5
TC7W139FU(TE12R) (TOSHIBA)CHIP PACKAGE
C-MOS 2 to 4 LINE DECODER WITH ENABLE
—TOP VIEW—
(SCALE 5/1)
V
DD
1 8
(+2 to +6V)
2 7
3 6
GND 4 5
F TYPE
1 7
A Y0
6
2
B Y1
5
Y2
3
Y3
INPUTS OUTPUTS
SELECTED
SELECT
OUTPUT
Y0 Y1 Y2 Y3
B A
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0
0 ; LOW LEVL
1 ; HIGH LEVEL
2-28
A A
Y
Y =
B B
Y = A + B = A • B
A B Y
0 0 1
0 1 0
1 0 0
0 ; LOW LEVEL
1 1 0
1 ; HIGH LEVEL
1 7
A Y = A Y
3 5
6 2
Y = A
A Y
0 1
1 0
0 ; LOW LEVEL
1 ; HIGH LEVEL
1
A 7 A
2 Y = Y
B B
5
3
6
Y = A • B = A + B
A B Y
0 0 0
0 1 0
1 0 0
0 ; LOW LEVEL
1 1 1
1 ; HIGH LEVEL
(SCALE 5/1)
V
DD
1 8
(+2 to +6V)
2 7
3 6
GND 4 5
FU TYPE
Y0
Y1
Y2
Y3
TC7W32FU (TOSHIBA)CHIP PACKAGE
TC7W32FU(TE12R)
C-MOS DUAL 2-INPUT OR GATE
—TOP VIEW—
1
V
DD A
1 8 7 Y
(+2 to +6 V)
2
B
2 7
3 6
5
3
6
GND 4 5
A B
0 0
0 1
1 0
1 1
TC7W74FU (TOSHIBA)CHIP PACKAGE
TC7W74FU(TE12R)
TC7WH74FU(TR12R) (TOSHIBA)CHIP PACKAGE
C-MOS D-TYPE FLIP-FLOPS WITH PRESET AND CLEAR
—TOP VIEW—
7
1 8 V
DD
PR
2 5
2 7
D Q
1
6
3
3
Q
GND 4 5
CLR
(SCALE 3/1)
6
TYPE V
DD INPUTS
7W74F
CLR
PR CK
+2 to +6V
7W74FU
0
1 X
+2 to +5.5V
7WH74FU
1
0 X
X
0
0
1 1
1 1
1 1
0 ; LOW LEVEL
1 ; HIGH LEVEL
X ; DON'T CARE
TL064CPW (TI)FLAT PACKAGE
TL064CPW-E05
OPERATIONAL AMPLIFIER
(J FET INPUT)
—TOP VIEW—
1 14
_ + + _
2 13
3 12
V V
CC EE
4 11
(+18V) (-18V)
5 10
6 _ + 9
7 8
UPA101G (NEC)FLAT PACKAGE
UPA101G-E2
TRANSISTOR ARRAY
—TOP VIEW—
8 7 6 5
1 2 3 4
A
Y
B
Y = A + B = A • B
Y
0
1
1
0 ; LOW LEVEL
1
1 ; HIGH LEVEL
OUTPUTS
FUNCTION
D Qn+1 Qn+1
X 0 1 CLEAR
X 1 0 PRESET
X 1 1 –
0 0
1 –
1 1
0 –
X
Qn
Qn NO CHANGE
BVP-900
BVP-900P