HPE Edgeline EL4000 User Manual page 51

NOTE:
For other specifications, see 'PXI-1 Hardware Specification' at the PXI Systems Alliance website
(http://www.pxisa.org/userfiles/files/Specifications/PXIHWSPEC22.pdf).
100 MHz system reference clock: PXIe_CLK100 and PXIe_SYNC100
Specification
Maximum slot-to-slot skew
Accuracy
Maximum jitter
Duty factor for PXIe_CLK100
Absolute single-ended voltage swing (when each
line in the differential pair has 50 W termination to
1.30 V or Thévenin equivalent)
NOTE:
For other specifications, see 'PXI-5 PXI Express Hardware Specification' at the PXI Systems
Alliance website (http://www.pxisa.org/userfiles/files/Specifications/
PXIEXPRESS_HW_SPEC_R1.PDF).
External 10 MHz reference out (SMA on front panel of chassis)
Specification
Accuracy
Maximum jitter
Output amplitude
Output impedance
External clock source
Specification
Frequency
Input amplitude
Front panel BNC
Front panel SMA input impedance
Value
200 ps
±25 ppm max (guaranteed over the operating
temperature range)
5 ps RMS phase jitter (10 Hz to 12 kHz range); 5
ps RMS phase jitter (12 kHz to 20 MHz range)
45% to 55%
400 mV to 1,000 mV
Value
±25 ppm max (guaranteed over the operating
temperature range)
5 ps RMS phase jitter (10 Hz to 1 MHz range)
1 VPP ±20% square wave into 50 Ω 2 VPP
unloaded
50 Ω ±5 Ω
Value
10 MHz ±100 PPM
—
200 mVPP to 5 VPP square-wave or sine-wave
50 Ω ± 5 Ω
Specifications 51