The Electrocardiogram - STMicroelectronics STM32 Cortex-M3 Manual

4.16.3 Pinning
2 Electrocardiogram (Ecg) Signals
SPI1
Wire GPIO Pin
NSS PA4 20
SCK PA5 21
The Electrocardiogram (Ecg)
MISO PA6 22
MOSI PA7 23
• Ecg: electrical manifestation of heart activity recorded
from the body surface
• monitoring of heart rate
The Ecg signal can be recorded fairly easily with surface
electrodes placed on the limbs and/or the chest, see pages
below.
RM0008
23.3 SPI functional description
23.3.1 General description
The block diagram of the SPI is shown in
Figure 207. SPI block diagram
Josef Goette
Usually, the SPI is connected to external devices through 4 pins:
●
●
●
●
A basic example of interconnections between a single master and a single slave is
46
illustrated in
Figure 4.23: SPI Connection between a Master a Slave
Address and data bus
Read
Rx buffer
MOSI
Shift register
MISO
Tx buffer
Write
SCK
Baud rate generator
2
Master control logic
NSS
Figure 4.24: SPI Driver
MISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode
and receive data in master mode.
MOSI: Master Out / Slave In data. This pin can be used to transmit data in master
mode and receive data in slave mode.
SCK: Serial Clock output for SPI masters and input for SPI slaves.
NSS: Slave select. This is an optional pin to select master/ slave mode. This pin acts as
a 'chip select' to let the SPI master communicate with slaves individually and to avoid
contention on the data lines. Slave NSS inputs can be driven by standard I/O ports on
the master Device. The NSS pin may also be used as an output if enabled (SSOE bit)
and driven low if the SPI is in master configuration. In this manner, all NSS pins from
devices connected to the Master NSS pin see a low level and become slaves when
they are configured in NSS hardware mode.
Figure 208.
Doc ID 13902 Rev 9
1 Intro
SPI2
Wire GPIO
NSS PB12
SCK PB13
MISO PB14
MOSI PB15
Serial peripheral interface (SPI)
Figure 207.
SPI_CR2
TXE RXNE ERR
0
IE IE IE
LSB first
SPI_SR
MOD
CRC
BSY OVR
ERR
F
Communication
control
BR[2:0]
LSB
SPE BR2 BR1 BR0
FIRST
SPI_CR1
BIDI CRC CRC
BIDI
DFF
MODE OE EN Next
4 Peripherals
Pin
33
34
35
36
6–16
TXDM RXDM
0
SSOE
AEN AEN
TXE RXNE
0 0
0
1
MSTR CPOL CPHA
2009
RX
SSM SSI
ONLY
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