External Interrupts (Irq); Configuration; Functionality - STMicroelectronics STM32 Cortex-M3 Manual

4.10 External Interrupts (IRQ)

4.10 External Interrupts (IRQ)
Pin PA0 is configured to generate an external interrupt. Pressing this button will toggle
extInt
a LED.
One of the key improvements of the Cortex core over the earlier ARM CPUs is its interrupt struc-
ture and exception handling. The ARM7 and ARM9 cores had two interrupt lines: The fast in-
terrupt and the general purpose interrupt line. These two interrupt lines had to support all of
the interrupt sources within a given manufacturer's microcontroller. How this was done varied
according to the implementation, so while the techniques used were broadly the same, the imple-
mentation differed between manufacturers.
Since the interrupt scheme is implemented in the Cortex-M3 core, the way of operating is for all
microcontroller s using this core equal.
4.10.1 Configuration
In the configuration wizard (see Figure 4.11) the external interrupts have to be enabled and con-
figured to a input pin.
Note that this input in the GPIO section as well has to be configured as an input!

4.10.2 Functionality

An event (rising or/and falling edge, according to the configuration) on EXTI0 will call the func-
tion
void EXTI0 IRQHandler(void)
check which ISR is pending by reading the pending register EXTI PR. At the end of the ISR you
have to clear the pending ISR in the EXTI PR. See Listing
void EXTI0 IRQHandler ( void )
i f ( EXTI PR & (1
// your ISR code here
40
EXTI PR = (1
Lukas Kohler
Figure 4.11: External Interrupt Configuration Wizard
. In this function, the interrupt service routine (ISR) first
Listing 4.8: ISR
0) )
0) ;
4.8 for an ISR example.
// EXTI0 i n t e r r u p t pending ?
// c l e a r pending i n t e r r u p t
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35