Sony DFR-E3000 Maintenance Manual page 71

[|IC|]
CXD8323Q (SONY)
SDIF-2 DIGITAL INPUT
—TOP VIEW—
52
53
54
55
56
57
58
59
60
61
62
63
64
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO. NO.
1 — NC 17 — NC 33
2 — NC 18 — NC 34
3 O PO23 19 O PO10 35
4 O PO22 20 O PO9 36
5 I/O PO21 21 O PO8 37
6 I/O PO20 22 O PO7 38
7 I/O PO19 23 O PO6 39
8 O PO18 24 O PO5 40
9 O PO17 25 — GND 41
10 — GND 26 — V 42
CC
11 O PO16 27 O PO4 43
12 O PO15 28 O PO3 44
13 O PO14 29 O PO2 45
14 O PO13 30 O PO1 46
15 O PO12 31 O PO0 47
16 O PO11 32 — NC 48
INPUTS
CK : 192FS OR 256FS MASTER CLOCK
CKMOD : MASTER CLOCK SELECTION
(L = 256FS, H = 192FS)
CS : CHIP SELECT INPUT FOR PARALLEL OUTPUT
OE : OUTPUT ENABLE INPUT FOR PARALLEL OUTPUT
RESET : TEST RESET INPUT
(NORMALLY FIXED AT L)
SCK : SERIAL OUTPUT BIT CLOCK
SEL0 : OUTPUT CHANNEL SELECT 0 IN THE PARALLEL
OUTPUT MODE
SEL1 : OUTPUT CHANNEL SELECT 1 IN THE PARALLEL
OUTPUT MODE
SI0 - SI3 : SDIF-2 SERIAL SIGNAL
SPSEL : OUTPUT MODE SETTING
(L = PARALLEL OUTPUT, H = SERIAL OUTPUT)
UBO - UB3 : USER'S BIT INPUT
(UB0 BIT25, UB3 BIT28)
WCK : WORD CLOCK
OUTPUTS
FO0 - FO5 : FLAG OUTPUT WHEN BLOCK FLAG BIT IS H
FO0...EMPHASIS (LOW)
FO1...EMPHASIS (HIGH)
FO2...DUBBING PROHIBIT
FO3...AUDIO/NON AUDIO
FO4...BLOCL FLAG BIT
FO5...DIN ACTIVE (H : ACTIVE)
PO0 - PO23 : WHEN PARALLEL OUTPUT MODE (SPSEL = L)
DIGITAL DATA (PO0 : LSB, PO23 : MSB)
WHEN SERIAL OUTPUT MODE (SPSEL = H)
PO23 : CH0, 1 SERIAL DATA
PO22 : CH2, 3 SERIAL DATA
PO21 : MSB/LSB FIRST SETTING
(L = MSB 1ST, H = LSB 1ST)
PO20 : DATA RIGHT JUSTIFICATION,
LEFT JUSTIFICATION SETTING
(L = LEFT JUSTIFICATION, H = RIGHT JUSTIFICATION)
PO19 : UB0 - UB3, FI0 - FI3 OUTPUT
METHOD SETTING
(L = SERIAL OUTPUT, H = PARALLEL OUTPUT)
OTHER
NC : NO CONNECTION
DFR-E3000
32
31
30
29
28
27
26
25
24
23
22
21
20
PIN
I/O SIGNAL I/O SIGNAL
NO.
— NC 49 I SEL1
— NC 50 I SEL0
— NC 51 I OE
— NC 52 I CS
— NC 53 I SI3
O UB3 54 I SI2
O UB2 55 I SI1
O UB1 56 I SI0
O UB0 57 — GND
— GND 58 — V
CC
O FO5 59 I CK
O FO4 60 I WCK
O FO3 61 I SCK
O FO2 62 I CKMOD
O FO1 63 I SPSEL
O FO0 64 I RESET
56
SI0
S P CONV
LATCH
55
SI1
S P CONV
LATCH
54
SI2
S P CONV
LATCH
53
SI3
S P CONV
LATCH
59
CK
TIMING
60
WCK
62 GEN
CKMOD
61, 63, 52 - 49, 64
7
SCK, SPSEL,
CS, OE,
SEL0, SEL1, RESET
EPC2LC20 (ALTERA)
CONFIGURATION EPROM
—TOP VIEW—
DCLK V
4 18 PP
V SEL 5 17 NC
CC
NC NC
6 16
NC 7 15 NC
OE 8 14 V SEL
PP
31 - 27, 24 - 19,
16 - 11, 9 - 3
24
PO0 - PO23
LATCH
P S CONV
41 - 38,
MUX
48 - 43
10
UB0 - UB3
FO0 - FO5
INPUTS
CS
: CHIP SELECT
OE : OUTPUT ENABLE
TD : JTAG DATA
TCK : JTAG CLOCK
TMS : JTAG MODE SELECT
V SEL : MODE SELECT FOR V SUPPLY
CC CC
V SEL : MODE SELECT FOR V
PP PP
OUTPUTS
CASC
: CASCADE SELECT
DATA : DATA
INIT-CONFI : INITIATE CONFIGURATION
TD : JTAG DATA
INPUT/OUTPUT
DCLK : CLOCK
OTHER
NC : NO CONNECTION
IC
4-3