Precautions; Restrictions On Debugging - Epson S5U1C17001H User Manual

8 Precautions

8.1 restrictions on Debugging

The debugging using the S5U1C17001H is subject to the restrictions specified below.
Operation of the internal peripheral circuits
The peripheral circuits of the target S1C processor stop operating when the debugger (gdb.exe) on the host
computer is ready to accept commands, that is, unless the target program is running. For this reason, the periph-
eral circuits do not operate in real time when the target program is executed in the single-step mode. For details
on single-step execution, refer to the "Debugger" section in the "S5U1C17001C Manual (C Compiler Package
for S1C17 Family)".
Interrupts when the target program is not running
If an interrupt request to the S1C Core is generated by the target system when the target program is not running,
interrupt processing is paused. The interrupt that has been paused is serviced immediately before the target
program is executed or immediately after one instruction is executed after the debugger (gdb.exe) on the host
computer has directed that the target program be executed.
Interrupts when the target program is executed in a single step
If an interrupt request to the S1C Core is generated by the target system during single-step execution of the
target program, including functions and subroutines (STEP), the interrupt request is paused. During single-step
execution of the target program, not including functions and subroutines (NEXT), an interrupt request received
within a function or subroutine is serviced without being paused and an interrupt received in other parts of the
program is paused as with the STEP command. The interrupt that has been paused is serviced immediately be-
fore the target program is executed or immediately after one instruction is executed after the debugger (gdb.exe)
on the host computer has directed that the target program be executed. For details on single-step execution (STEP
and NEXT), refer to the "Debugger" section in the "S5U1C17001C Manual (C Compiler Package for S1C17
Family)".
execution counter
The execution counter is capable of measuring execution times up to 6515 hours with a ±1 µs of measurement
error. A 3 µs or less of program execution time cannot be measured correctly.
The counter is also used for clocking of the lapse of time break function, therefore, execution times cannot be
measured when the lapse of time break function is used.
reset sequence
The sequence from when the S5U1C17001H is powered on until the target program is executed is entirely dif-
ferent from that of the actual S1C processor.
However, a sequence for the reset request input from the target system while the target program is being ex-
ecuted is the same as that for the actual S1C processor.
Regarding the reset sequence in the actual S1C processor, refer to the technical manual of each model.
Break functions when a reset request is accepted
If a reset request (reset input or reset interrupt from the watchdog timer) is accepted while the S1C processor
on the target system is executing the target program in normal mode, the hardware PC break and software PC
break functions are disabled. It will be enabled again when the S1C processor enters debug mode.
I/O memory dump by the S5U1C17001H
Note that some S1C peripheral circuits may change the control register status due to their specifications when
the I/O memory is read using the memory dump function of the S5U1C17001H or when the target program ex-
ecution is suspended.
For details on the memory dump function, refer to the "Debugger" section in the "S5U1C17001C Manual (C
Compiler Package for S1C17 Family)".
S5U1C17001H USer ManUal
(ICD MInI Ver. 1.0)
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8 PreCaUTIOnS
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