Pll Circuits - Icom IC-F14 Service Manual Addendum

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL output
compares the phase of the divided VCO frequency to the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the TX/RX VCO circuits (TX: Q13,
D16, D17, D21; RX: Q14, D19, D20, D22). The oscillated
signal is amplified at the buffer amplifiers (Q11, Q12) and
then applied to the PLL IC (IC4, pin 8) after being passed
through the low-pass filter (L32, C206–C208).
The phase detected signal outputs from pins 15 and 16, and
is then applied to the charge pump (Q39, Q40). The signal
passes through the loop filter (C146, C147, C149, R95–
R97), and is then applied to the TX and RX VCO circuits as
a lock voltage.
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The entered
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided signal
is detected on phase at the phase detector using the refer-
ence frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
PLL CIRCUITS
Buffer
Q18
"LVIN" signal to the CPU
(IC13, pin 64)
45.9 MHz 2nd LO
signal to the FM IF IC
Tripler
(IC1, pin 2)
Q19
RX VCO
Q14, D19, D20, D22
TX VCO
Loop
Q13, D16, D17, D21
filter
Charge
Pump
Q39, Q40
15
Phase
detector
16
Programmable
divider
2
3
4-3-2 VCO CIRCUIT
The VCO circuit contains a separate RX VCO (Q14, D19,
D20) and TX VCO (Q13, D16, D17). The oscillated signal
is amplified at the buffer amplifiers (Q10, Q12) and is then
applied to the T/R switch (D14 for TX, D15 for RX). Then the
receive 1st LO (RX) signal is applied to the 1st mixer circuit
(Q3) and the transmit (TX) signal to the pre-drive amplifier
(Q9).
A portion of the signal from the buffer amplifier (Q12) is fed
back to the PLL IC (IC4, pin 8) via the buffer amplifier (Q11)
and low-pass filter (L32, C206–C208) as the comparison
signal.
Buffer
Q12
IC4 MB15A02
Programmable
Prescaler
counter
Shift register
1
15.3 MHz
4 - 4
D15
Buffer
to 1st mixer circuit
Q10
D14
to transmitter circuit
Buffer
Q11
LPF
8
14
SCK
15
SO
16
PLST
X2