Pll Circuits - Icom IC-F43TR Service Manual

4-2-2 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.
The AF signals from the D/A converter (IC12, pin 3) change
the reactance of varactor diode (D12) to modulate the oscil-
lated signal at the TX VCO circuit (Q16, D10). The modulat-
ed VCO signal is amplified at the buffer amplifiers (Q15,
Q29) and is then applied to the drive amplifier circuit via the
T/R switch (D16).
The CTCSS/DTCS signals ("CENC0", "CENC1", "CENC2"
from the CPU (IC22, pins 13, 15, 16) pass through the low-
pass filter (IC6, pins 12, 14), and are then applied to the D/A
converter via the "TONC" line (IC12, pin 12). The output sig-
nal from the D/A converter (IC12, pin 11) are mixed with
"MOD" signal at the low-pass filter (IC6), and are then
applied to the D/A converter again (IC12, pin 4).
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
(PA UNIT)
The drive/power amplifier circuits amplify the VCO oscillat-
ing signal to an output power level.
The signal from the VCO circuit passes through the T/R
switch (MAIN unit; D16), and is amplified at the YGR (Q703,
Q704), drive (Q702), power (Q701) amplifiers to obtain 4 W
of RF power (at 7.2 V DC).
The amplified signal is passed through the low-pass filter
(L704, C711, C712, C713, C755), power detector (D702,
D703), antenna switching circuit (D701) and other low-pass
filters (PA unit; L709, C744, C745), (ANT unit; L801, L802,
C802, C803, C804, C805), and is then applied to the anten-
na connector (CHASSIS unit; J1).
The bias current of the drive (Q702) and power (Q701)
amplifiers are controlled by the APC circuit.
• APC CIRCUIT
VCC
T5V
Q704
YGR
RF signal
amp.
from PLL circuit
–
TMUT
D29
T2
+
APC control circuit
Q703
YGR Driver
amp. amp.
IC16
APC
amp.
4-2-4 APC CIRCUIT (PA AND MAIN UNITS)
The APC circuit protects the drive and power amplifiers from
excessive current drive, and selects output power of HIGH
or LOW.
The power detector circuit (PA unit; D702, D703) detects the
transmit power output level and converts it into DC voltage.
The output voltage is at a minimum level when the antenna
impedance is matched at 50 Ω and is increased when it is
mismatched.
The detected voltage is applied to the differential amplifier
(MAIN unit; IC16; pin 3), and the "T2" signal from the D/A
converter (MAIN unit; IC12, pin 23), controlled by the CPU
(MAIN unit; IC22), is applied to the other input for reference.
When antenna impedance is mismatched, the detected volt-
age exceeds the power setting voltage. Then the output volt-
age of the differential amplifier (MAIN unit; IC16, pin 4) con-
trols the input current of the drive (PA unit; Q702) and power
(PA unit; Q701) amplifiers to reduce the output power.

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the TX/RX VCO circuits (Q16, Q17,
D9-D13). The oscillated signal is amplified at the buffer
amplifiers (Q14, Q15) and then applied to the PLL IC (IC21,
pin 6) after being passed through the low-pass filter (L32,
C206, C208).
PA unit
Q702
Q701
Power
amp.
4 - 3
ANT
LPF
LPF
SW
D701
D702
to ANT unit
D703