Ic Description - Aiwa XD-DV370 Service Manual

IC DESCRIPTION - 11/11(ZIVA4.1) - 5/5
Pin No. Pin Name
189 VDD_2.5
190 RESERVED
191 VSS
192 VDD_3.3
193 ~ 196 RESERVED
197 HDATA7
198 VSS
199 HDATA6
200 HDATA5
201 HDATA4
202 HDATA3
203 HDATA2
204 VDD_3.3
205 VSS
206 HDATA1
207 HDATA0
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208 CS
I/O
– 2.5-V supply voltage for core logic.
I Tie to VSS or VDD_3.3.
– Ground for core logic and I/O signals.
– 3.3-V supply voltage for I/O signals.
I Tie to VSS or VDD_3.3.
HDATA[7] is the 8-bit bi-directional host data bus through which the host writes data to the
I/O decoder Code FIFO. MSB of the 32-bit word is written first. The host also reads and writes the
decoder internal registers and local SDRAM/ROM via HDATA[7].
– Ground for core logic and I/O signals.
I/O
I/O
HDATA[6 ~ 2] is the 8-bit bi-directional host data bus through which the host writes data to the
I/O
decoder Code FIFO. MSB of the 32-bit word is written first. The host also reads and writes the
I/O decoder internal registers and local SDRAM/ROM via HDATA[6 ~ 2].
I/O
– 3.3-V supply voltage for I/O signals.
– Ground for core logic and I/O signals.
I/O HDATA[1, 0] is the 8-bit bi-directional host data bus through which the host writes data to the
decoder Code FIFO. MSB of the 32-bit word is written first. The host also reads and writes the
I/O decoder internal registers and local SDRAM/ROM via HDATA[1, 0].
Host chip select. Host asserts CS to select the decoder for a read or write operation. The falling
I
edge of this signal triggers the read or write operation.
Description
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