Aiwa XD-DV370 Service Manual page 51

IC DESCRIPTION - 4/11 (GM72V161621ET-7)-2/2
Pin No. Pin Name
34 CKE
35 CLK
36 UDQM
37 NC
38 VCCQ
39 MD8
40 MD9
41 VSSQ
42 MD10
43 MD11
44 VCCQ
45 MD12
46 MD13
47 VSSQ
48 MD14
49 MD15
50 GND
I/O
This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
I edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-
down and clock suspend modes.
I CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge.
DQM controls input/output buffers.
- Read operation: If DQM is High, The output buffer becomes High-Z. If the DQM is Low, the
I output buffer becomes Low-Z.
- Write operation: If DQM is High, the previous data is held (the new data is not written). If
DQM is Low, the data is written.
– Not used
– 3.3 V is applied. (VCCQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
I/O
DRAM.
– Ground is connected. (VSSQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
I/O
DRAM.
– 3.3 V is applied. (VCCQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
I/O
DRAM.
– Ground is connected. (VSSQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
I/O
DRAM.
– Ground is connected. (VSS is for the internal circuit.)
Description
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