Aiwa XD-DV370 Service Manual page 50

IC DESCRIPTION - 4/11 (GM72V161621ET-7)-1/2
Pin No. Pin Name
1 VCC
2 DQ0
3 DQ1
4 VSSQ
5 DQ2
6 DQ3
7 VCCQ
8 DQ4
9 DQ5
10 VSSQ
11 DQ6
12 DQ7
13 VCCQ
14 LDQM
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15 MWE
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16 CAS
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17 RAS
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18 CS1
19 MA11
20 MA10
21 MA0
22 MA1
23 MA2
24 MA3
25 VCC
26 GND
27 MA4
28 MA5
29 MA6
30 MA7
31 MA8
32 MA9
33 NC
I/O
– 3.3 V is applied. (VCC is for the internal circuit.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
I/O
DRAM.
– Ground is connected. (VSSQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
I/O
DRAM.
– 3.3 V is applied. (VCCQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
I/O
DRAM.
– Ground is connected. (VSSQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
I/O
DRAM.
– 3.3 V is applied. (VCCQ is for the output buffer.)
DQM controls input/output buffers.
- Read operation: If DQM is High, The output buffer becomes High-Z. If the DQM is Low, the
I output buffer becomes Low-Z.
- Write operation: If DQM is High, the previous data is held (the new data is not written). If
DQM is Low, the data is written.
Although these pin names are the same as those of conventional DRAMs, they function in a
I different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operation section.
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When CS is Low, the command input cycle becomes valid. When CS is high, all inputs are
I
ignored. However, internal operations (bank active, burst operations, etc.) are held.
A11 is a bank select signal (BS). The memory array of the GM72V161621ET/ELT Series is
I divided into bank 0 and bank 1. GM72V161621ET/ELT Series contain 2048 row x 256 column x
16bits. If A11 is Low, bank 0 is selected, and if A11 is High , bank 1 is selected.
Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active command
cycle CLK rising edge. Column address is determined by A0 to A7 level at the read or write
command cycle CLK rising edge. And this column address becomes burst access start address.
I
A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks
are precharged. But when A10 = Low at the precharge command cycle, only the bank that is
selected by A11 ( BS) is precharged.
– 3.3 V is applied. (VCC is for the internal circuit.)
– Ground is connected. (VSS is for the internal circuit.)
Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active command
cycle CLK rising edge. Column address is determined by A0 to A7 level at the read or write
command cycle CLK rising edge. And this column address becomes burst access start address.
I
A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks
are precharged. But when A10 = Low at the precharge command cycle, only the bank that is
selected by A11 ( BS) is precharged.
– Not used.
Description
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