Aiwa XD-DV370 Service Manual page 63

IC DESCRIPTION - 11/11(ZIVA4.1) - 1/5
Pin No. Pin Name
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1 RD
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2 R/W
3 VDD_3.3
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4 WAIT
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5 RESET
6 VSS
7 VDD_3.3_5
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8 INT
9 ~ 12 NC
13 VDD_2.5
14 VSS
15 ~ 18 NC
19 VSS
20 VDD_3.3_5
VDATA0 ~
21 ~ 28
VDATA7
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29 VSYNC
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30 HSYNC
31 VSS
32 VDD_3.3_5
33 ~ 35 NC
36 VDD_2.5
37 VSS
38 ~ 42 NC
43 PIO0
44 VSS
45 VDD_3.3_5
46 ~ 52 PIO1 ~ PIO7
53, 54 MDATA0, MDATA1
55 VDD_3.3
56 VSS
I/O
I Read strobe in I mode. Must be held HIGH in M Mode.
Read/write strobe in M mode. Write strobe in I mode. Host asserts R/W LOW to select Write and
I
LOW to select Read for M Mode only.
– 3.3-V supply voltage for I/O signals.
Transfer not complete / data acknowledge. Active LOW to indicate host initiated transfer is not
___________
complete. WAIT is asserted after the falling edge of CS and reasserted when decoder is ready to
O
complete transfer cycle. Open drain signal, must be pulled-up via 1k ohm to 3.3 volts. Driven
high for 10 ns before tristate.
Active Low Reset. Assert for at least 5-milliseconds in the presence of clock to reset the entire
I
chip.
– Ground for core logic and I/O signals.
– 3.3/5-V supply voltage for I/O signals.
Host interrupt. Open drain signal, must be pulled-up via 4.7k ohm to 3.3 volts. Driven high for
O
10 ns before tristate.
O Not used
– 2.5-V supply voltage for core logic.
– Ground for core logic and I/O signals.
O Not used
– Ground for core logic and I/O signals.
– 3.3/5-V supply voltage for I/O signals.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up, the decoder
O does not drive VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-
state VDATA.
Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the first
_____________
HSYNC after the falling edge of VSYNC. VSYNC can accept vertical synchronization or top/
I/O
bottom field notification from an external source. (VSYNC HIGH = bottom field. VSYNC LOW
= Top field)
Horizontal sync. The decoder begins outputting pixel data for a new horizontal line after the
I/O
falling (active) edge of HSYNC.
– Ground for core logic and I/O signals.
– 3.3/5-V supply voltage for I/O signals.
O Not used
– 2.5-V supply voltage for core logic.
– Ground for core logic and I/O signals.
O Not used
I/O Programmable I/O pins.
– Ground for core logic and I/O signals.
– 3.3/5-V supply voltage for I/O signals.
I/O Programmable I/O pins.
I/O SDRAM Data
– 3.3-V supply voltage for I/O signals.
– Ground for core logic and I/O signals.
Description
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