Aiwa XD-DV370 Service Manual page 64

IC DESCRIPTION - 11/11(ZIVA4.1) - 2/5
Pin No. Pin Name
57 ~ 62 MDATA2 ~ MDATA7
63 MDATA15
64 VDD_3.3
65 VSS
66 MDATA14
67 VDD_2.5
68 VSS
69 ~ 73 MDATA13 ~ MDATA9
74 VDD_3.3
75 VSS
76 MDATA8
77 LDQM
78 SD-CLK
79 CLKSEL
80, 81 MADDR9, MADDR8
82 VDD_3.3
83 VSS
84 ~ 86 MADDR7 ~ MADDR5
87 VDD_2.5
88 VSS
89 MADDR4
__________
90 MWE
______________
91 SD-CAS
92 VDD_3.3
93 VSS
______________
94 SD-RAS
_____________
95 SD-CS0
_____________
96 SD-CS1/MADDR11
____________
97 SD-BS
98 MADDR10
99 MADDR0
100 VDD_3.3
101 VSS
102 ~ 104 MADDR1 ~ MADDR3
105 VSS ADC
106 ~ 111 NC
112 DAI XCK
113 DAI-LRCK
114 DAI-BCK
115 VDD_3.3
116 VSS
I/O
I/O SDRAM Data
I/O SDRAM Data
– 3.3-V supply voltage for I/O signals.
– Ground for core logic and I/O signals.
I/O SDRAM Data
– 2.5-V supply voltage for core logic.
– Ground for core logic and I/O signals.
I/O SDRAM Data
– 3.3-V supply voltage for I/O signals.
– Ground for core logic and I/O signals.
I/O SDRAM Data
O SDRAM Lower or Upper Mask
O SDRAM Clock
I Selects SYSCLK or VCLK as clock source. Normal operation is to tie HIGH.
O SDRAM Address
– 3.3-V supply voltage for I/O signals.
– Ground for core logic and I/O signals.
O SDRAM Address
– 2.5-V supply voltage for core logic.
– Ground for core logic and I/O signals.
O SDRAM Address
O SDRAM Write Enable
O Active LOW SDRAM Column Address
– 3.3-V supply voltage for I/O signals.
– Ground for core logic and I/O signals.
O Active LOW SDRAM Row Address
O Active LOW SDRAM Chip Select 0
O Active LOW SDRAM Chip Select 1 or use as MADDR11 for larger SDRAM (64 Mbits).
O SDRAM Bank Select
O SDRAM Address
O SDRAM Address
– 3.3-V supply voltage for I/O signals.
– Ground for core logic and I/O signals.
O SDRAM Address
I Not used
– Not used
I Tie to VSS or VDD_3.3
I PCM left/right clock.
I PCM input bit clock.
– 3.3-V supply voltage for I/O signals.
– Ground for core logic and I/O signals.
Description
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