Aiwa XD-DV370 Service Manual page 52

IC DESCRIPTION - 5/11(PLL1700E)-1/1
Pin No. Pin Name
1 D PLL L
2 MODE
3 VDD
4 GND
5 XT2
6 XT1
7 GNDP
8 VDDP
9 RSV
10 MCKO
11 MPEG CLK
12 SCKO1 MCK
13 SCKO4
14 SCKO2
15 GNDB
16 VDDB
17 DA XCK
18 RESET
19 S DATA
20 S CLK
I/O
Latch Enable for Software Mode/Sampling Rate Selection for Hardware Mode. When MODE
I
pin is LOW, ML is selected.(1)
Mode Control Select. When this pin is HIGH, device is operated in hardware mode using SR0
I (pin 1), FS0 (pin 19), and FS1 (pin 20). When this pin is LOW, device is operated in software
mode by three-wire interface using ML (pin 1), MD (pin 19) and MC (pin 20).(1)
– Digital Power Supply, +5V.
– Digital Ground.
27MHz Crystal. When an external 27MHz clock is applied to XT1 (pin 6), this pin must be
–
connected to GND.
I 27MHz Oscillator Input/External 27MHz Input.
– Ground for PLL.
– Power Supply for PLL, +5V.
– Reserved. Must be left open.
O 27MHz Output.
O Inverted 27MHz Output.
O Fixed 33.8688MHz Clock Output.
O 768f Clock Output.
S
O 256f Clock Output.
S
– Digital Ground for VDDB.
– Digital Power Supply for Clock Output Buffers, +3.3V.
384f Output. This output has been optimized for the lowest jitter and should be connected to the
S
O
audio DAC(s).
I Reset. When this pin is LOW, device is held in reset.(1)
Serial Data Input for Software Mode/Sampling Frequency Selection for Hardware Mode. When
I
MODE pin is LOW, MD is selected.(1)
Shift Clock Input for Software Mode/Sampling Frequency Selection for Hardware Mode. When
I
MODE pin is LOW, MC is selected.(1)
Description
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