Aiwa XD-DV370 Service Manual page 47

IC DESCRIPTION - 1/11 (SSI33P3721)-2/2
Pin No. Pin Name
36 PI
37 DFT
38 TPH
39 TZC
40 TEI
41 TE
42 FE
43 CE
44 BYP2
45 HOLD2
46 SCLK
47 SDATA
48 SDEN
49 HOLD1
50 VNA
51 FNN
52 FNP
53 DIP
54 DIN
55 RX
56 BYP
57 SIGO
58 VPA
59 AIP
60 AIN
61 ATON
62 ATOP
63 CDRF
64 CDRFDC
I/O
PULL-IN SIGNAL OUTPUT: The summing signal output of A,B,C,D inputs for mirror
O
detection. Reference to VCI.
DEFECT OUTPUT: Pseudo CMOS output. When defect is detected, the DFT output goes high.
O
Also the servo AGC output can be monitored at this DFT pin, when CAR bit7-4 is '0011'.
– PI TOP HOLD PIN: An external capacitance is connected to VPB.
TRACKING ZERO CROSSING SIGNAL OUTPUT: Tracking zero crossing output. Pseudo
O
CMOS output.
TRACKING ERROR AC COUPLED INPUT: AC couple input for the tracking zero crossing
I
signal output.
O TRACKING ERROR SIGNAL OUTPUT: Tracking error output reference to VCI.
O FOCUSING ERROR SIGNAL OUTPUT: Focus error output reference to VCI.
O CENTER ERROR SIGNAL OUTPUT: Center error output reference to VCI.
– The Servo AGC integration capacitor CBYP2, is connected between BYP2 and VNB.
HOLD CONTROL: TTL compatible control pin which, when pulled high,disables the Servo
I
AGC charge pump and holds the Servo AGC amplifier gain as its present value. (open high)
SERIAL CLOCK: Serial clock CMOS input. The clock applied to this pin is synchronized with
I
the data applied to SDATA. (not to be left open)
SERIAL DATA: Serial data bidirectional CMOS pin. NRZ programming data for the internal
I/O
registers is applied to this input. (not to be left open)
SERIAL DATA ENABLE: Serial enable CMOS input. A high level input enables the serial port.
I
(not to be left open)
HOLD CONTROL: TTL compatible control pin which, when pulled high, disables the RF AGC
I
charge pump and holds the RF AGC amplifier gain as its present value. (open high)
– Ground pin for the RF block and serial port.
O
DIFFERENTIAL NORMAL OUTPUTS: Filter normal outputs.
O
I
ANALOG INPUTS FOR RF SINGLE BUFFER: Differential analog inputs to the RF single-end
I output buffer and full wave rectifier.
REFERENCE RESISTOR INPUT: An external 12.1 or 8.2 k ohm, 1% resistor is connected from
– this pin to ground to establish a precise PTAT (proportional to absolute temperature) reference
current for the filter.
– The RF AGC integration capacitor CBYP, is connected between BYP and VPA.
O SINGLE-ENDED NORMAL OUTPUT: Single-ended RF output.
– Power supply pin for the RF block and serial port.
I
AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins.
I
O
DIFFERENTIAL ATTENUATOR OUTPUTS: Attenuator outputs.
O
I RF SIGNAL INPUT : Single-ended RF signal attenuator input pin.
O CD RF SIGNAL OUTPUT: Single-ended CD RF summing output.
Description
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