Table of Contents
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Features
8 channels of 24-bit DDX
amplification)
>100 dB of SNR and dynamic range
Selectable 32 kHz - 192 kHz input sample rates
6 channels of DSD/SACD input
Digital gain/attenuation +58 dB to -100 dB in
0.5-dB steps
Soft volume update
Individual channel and master gain/attenuation
plus channel trim (-10 dB to +10 dB)
Up to 10 independent 32-bit user
programmable biquads (EQ) per channel
Bass/treble tone control
Pre and post EQ full 8-channel input mix on all
8 channels
Dual independent limiters/compressors
Dynamic range compression
Automode™:
– 5-band graphic EQ
– 32 preset EQ curves (rock, jazz, pop, etc.)
– Automatic volume controlled loudness
– 5.1 to 2-channel downmix
– Simultaneous 5.1- and 2-channel downmix
outputs
– 3 preset volume curves
– 2 preset anti-clipping modes
– Preset movie nighttime listening mode
– Preset TV channel/commercial AGC mode
– 5.1, 2.1 bass management configurations
– 8 preset crossover filters
Individual channel and master soft/hard mute
Automatic zero-detect and invalid input mute
Automatic invalid input detect mute
Advanced PopFree operation
October 2009
Multi-channel digital audio processor with DDX
®
(direct digital
Doc ID 13855 Rev 4
Advanced AM interference frequency
switching and noise suppression modes
2
I
S output channel mapping function
Independent channel volume and DSP bypass
Channel mapping of any input to any
®
processing/DDX
DC blocking selectable high-pass filter
Selectable per-channel DDX
or binary PWM output
Max power correction for lower full-power THD
Variable per channel DDX
192 kHz internal processing sample rate, 24-bit
to 36-bit precision
Description
The STA309A is a single chip solution for digital
audio processing and control in multi-channel
applications. It provides output capabilities for
®
DDX
. In conjunction with a DDX
the STA309A provides high-quality,
high-efficiency, all digital amplification. The device
is extremely versatile, allowing inputs of most
digital formats including 6.1/7.1-channel and
192 kHz, 24-bit DVD-audio, DSD/SACD. In 5.1
applications the additional 2 channels can be
used for audio line-out or headphone drive. In
speaker mode, with 8 channel outputs in parallel,
the STA309A can deliver more than 1 W.
Table 1.
Device summary
Order code
STA309A
STA309A13TR
STA309A
TQFP64
channel
®
damped ternary
®
output delay control
®
power device,
Package
TQFP64
TQFP64
www.st.com
®
1/67
67
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Table of Contents
Related Manuals for ST STA309A
Summary of Contents for ST STA309A
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Page 1: Table 1. Device Summary
Dynamic range compression Description Automode™: – 5-band graphic EQ The STA309A is a single chip solution for digital – 32 preset EQ curves (rock, jazz, pop, etc.) audio processing and control in multi-channel – Automatic volume controlled loudness applications. It provides output capabilities for ®... -
Page 2: Table Of Contents
Contents STA309A Contents Block diagram ..........9 Pin connections . - Page 3 STA309A Contents 7.2.7 Configuration register G (0x06) ....... 31 7.2.8 Configuration register H (0x07) .
- Page 4 Contents STA309A 7.2.44 Tone control bypass (0x2B) ........46 7.2.45...
- Page 5 STA309A Contents Writing a single coefficient to RAM ......58 Writing a set of coefficients to RAM ......59 Equalization and mixing .
- Page 6 List of tables STA309A List of tables Table 1. Device summary ............1 Table 2.
- Page 7 STA309A List of tables Table 49. MV bits ..............37 Table 50.
- Page 8 Read mode sequence ........... . 17 Figure 6. Reference schematic for STA309A-based application ......18 Figure 7.
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Page 9: Block Diagram
STA309A Block diagram Block diagram Figure 1. Block diagram SCL SDA OUT1A/B LRCKI OUT2A/B BICKI SERIAL OUT3A/B OVERSAMPLING SDI12 DATA OUT4A/B SDI34 SYSTEM OUT5A/B SDI56 CONTROL OUT6A/B SDI78 OUT7A/B OUT8A/B VARIABLE TREBLE, VOLUME CHANNEL OVER- BASS, EQ LIMITING MAPPING LRCKO... -
Page 10: Pin Connections
Pin connections STA309A Pin connections Figure 3. Pin connection (top view) 59 58 57 56 53 52 51 50 49 OUT2_A OUT2_B SDI_78 OUT3_A SDI_56 OUT3_B SDI_34 OUT4_A SDI_12 OUT4_B LRCKI OUT5_A BICKI OUT5_B RESET OUT6_A PLLB OUT6_B 17 18 19 20 21... - Page 11 STA309A Pin connections Table 2. Pin description (continued) Type Name Description CMOS input buffer with Select address (I pull-down Bidirectional buffer: 5-V tolerant TTL schmitt trigger Serial data (I input; 3.3-V capable 2mA slew-rate controlled output. 5-V tolerant TTL schmitt...
- Page 12 Pin connections STA309A Table 2. Pin description (continued) Type Name Description 3.3-V capable TTL 16mA OUT2A PWM channel 2 output A output buffer 3.3-V capable TTL 16mA OUT1B PWM channel 1 output B output buffer 3.3-V capable TTL 16mA OUT1A...
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Page 13: Electrical Specification
STA309A Electrical specification Electrical specification Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Unit 3.3-V I/O power supply, pin VDD -0.5 3.3-V logic power supply, pin VDDA -0.5 Voltage on input pins -0.5 Voltage on output pins -0.5 Storage temperature °C... -
Page 14: Electrical Specifications
Electrical specification STA309A Electrical specifications The following specifications are valid for V = 3.3 V ± 0.3 V, V = 3.3 V ± 0.3 V and Tamb = 0 to 70 °C, unless otherwise stated Table 6. General interface electrical specifications... -
Page 15: Pin Description
LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. Device power-down (PWDN) Pulling PWDN low begins the power-down sequence which puts the STA309A into a low-power state. EAPD (pin 51) goes low approximately 30 ms later. -
Page 16: C Bus Operation
5.1.4 Data input During the data input the STA309A samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. -
Page 17: Write Operation
Following the START condition the master sends a device select code with the RW bit set to 0. The STA309A acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA309A again responds with an acknowledgement. -
Page 18: Application Reference Schematic
Application reference schematic STA309A Application reference schematic Figure 6. Reference schematic for STA309A-based application 18/67 Doc ID 13855 Rev 4... -
Page 19: Registers
STA309A Registers Registers Register summary Table 8. Register summary Addr Name Configuration 0x00 CONFA COS1 COS0 DSPB MCS2 MCS1 MCS0 0x01 CONFB Reserved SAIFB SAI3 SAI2 SAI1 SAI0 0x02 CONFC Reserved SAOFB SAO3 SAO2 SAO1 SAO0 0x03 CONFD CSZ4 CSZ3... - Page 20 Registers STA309A Table 8. Register summary (continued) Addr Name 0x1C C34IM Reserved C4IM2 C4IM1 C4IM0 Reserved C3IM2 C3IM1 C3IM0 0x1D C56IM Reserved C6IM2 C6IM1 C6IM0 Reserved C5IM2 C5IM1 C5IM0 0x1E C78IM Reserved C8IM2 C8IM1 C8IM0 Reserved C7IM2 C7IM1 C7IM0 Automode™...
- Page 21 STA309A Registers Table 8. Register summary (continued) Addr Name 0x38 C34OM Reserved C4OM2 C4OM1 C4OM0 Reserved C3OM2 C3OM1 C3OM0 0x39 C56OM Reserved C6OM2 C6OM1 C6OM0 Reserved C5OM2 C5OM1 C5OM0 0x3A C78OM Reserved C8OM2 C8OM1 C8OM0 Reserved C7OM2 C7OM1 C7OM0 User-defined coefficient RAM...
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Page 22: Register Description
S sample frequency and the input clock. MCS2 The STA309A supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, 192 kHz, and 2.8224 MHz DSD. Therefore, the internal clocks are: 65.536 MHz for 32 kHz 90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD... -
Page 23: Table 11. Interpolation Ratio Bits
I S sample frequency The STA309A has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 4 times, 2 times, or 1 time (pass-through). -
Page 24: Configuration Register B (0X01) - Serial Input Formats
The STA309A audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. STA309A always acts a slave when receiving audio input from standard digital audio components. Serial data for eight channels is provided... -
Page 25: Table 17. Sai And Saifb Serial Clock
STA309A Registers The table below lists the serial audio input formats supported by STA309A as related to BICKI = 32 , where sampling rate, fs = 32, 44.1, 48, 88.2, 96, 176.4, * fs, * fs, * fs 192 kHz. -
Page 26: Configuration Register C (0X02) - Serial Output Formats
SAO3 The STA309A features a serial audio output interface that consists of 8 channels. The serial audio output always acts as a slave to the serial audio input interface and, therefore, all output clocks are synchronous with the input clocks. The output sample frequency (fs) is also equivalent to the input sample frequency. -
Page 27: Configuration Register D (0X03)
STA309A Registers Table 20. SAO serial clock (continued) BICKI = BICKO SAO[3:0] Interface data format 0000 S data 0001 Left-justified data 0010 Right-justified 24-bit data 64 * fs 0011 Right-justified 20-bit data 0100 Right-justified 18-bit data 0101 Right-justified 16-bit data 7.2.4... -
Page 28: Configuration Register E (0X04)
Registers STA309A Table 24. CSZ definition CSZ[4:0] Compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size … … 11111 31 clock period compensating pulse size Table 25. MPC bit Name Description Max power correction: 1: enable STA50x correction for THD reduction near maximum power output. -
Page 29: Configuration Register F (0X05)
High-pass filter bypass bit: 1: bypass internal AC coupling digital high-pass filter The STA309A features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. -
Page 30: Table 30. Psl Bit
Registers STA309A Table 30. PSL bit Name Description Postscale link: 0: each channel uses individual postscale value 1: each channel uses channel 1 postscale value The Postscale function can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the postscale values can be linked to the value of channel 1 for ease of use and update the values faster. -
Page 31: Configuration Register G (0X06)
0: normal DDX operation. 1: AM2 reduction mode DDX operation. The STA309A features a 2 DDX processing modes that minimize the amount of noise generated in frequency range of AM radio. This second mode is intended for use when DDX is operating in a device with an AM tuner active. -
Page 32: Configuration Register H (0X07)
Registers STA309A Table 37. DCCV bit Name Description Distortion compensation variable enable: DCCV 0: uses preset DC coefficient. 1: uses DCC coefficient. Table 38. MPCV bit Name Description Max power correction variable: MPCV 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient 7.2.8... -
Page 33: Configuration Register I (0X08)
STA309A Registers Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the input data to each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. -
Page 34: Master Mute Register (0X09)
Registers STA309A Table 48. EAPD bit Name Description External amplifier power down: EAPD 0: external power stage power down active 1: normal operation 7.2.10 Master mute register (0x09) Reserved MMUTE 7.2.11 Master volume register (0x0A) Note: Value of volume derived from MVOL is dependent on AMV Automode volume settings. -
Page 35: Channel 5 Volume (0X0F)
STA309A Registers 7.2.16 Channel 5 volume (0x0F) C5V7 C5V6 C5V5 C5V4 C5V3 C5V2 C5V1 C5V0 7.2.17 Channel 6 volume (0x10) C6V7 C6V6 C6V5 C6V4 C6V3 C6V2 C6V1 C6V0 7.2.18 Channel 7 volume (0x11) C7V7 C7V6 C7V5 C7V4 C7V3 C7V2 C7V1 C7V0 7.2.19... -
Page 36: Channel 4 Volume Trim, Mute, Bypass (0X16)
C8VT1 C8VT0 The volume structure of the STA309A consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. There is also an additional offset for each channel called the channel volume trim. -
Page 37: Table 49. Mv Bits
STA309A Registers the volume setting, the master volume setting will not affect that channel. Each channel also contains a channel mute. If CnM = 1 a soft mute is performed on that channel. Table 49. MV bits MV[7:0] Volume offset from channel value... -
Page 38: Channel Input Mapping Channels 1 And 2 (0X1B)
Registers STA309A 7.2.28 Channel input mapping channels 1 and 2 (0x1B) Reserved C2IM2 C2IM1 C2IM0 Reserved C1IM2 C1IM1 C1IM0 7.2.29 Channel input mapping channels 3 and 4 (0x1C) Reserved C4IM2 C4IM1 C4IM0 Reserved C3IM2 C3IM1 C3IM0 7.2.30 Channel input mapping channels 5 and 6 (0x1D) -
Page 39: Auto1 - Automode™ Eq, Volume, Gc (0X1F)
STA309A Registers 7.2.32 AUTO1 - Automode™ EQ, volume, GC (0x1F) AMDM AMGC2 AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0 Table 53. AMEQ bits Name Description Biquad 2-6 mode is: 00: user programmable AMEQ[1:0] 01: preset EQ - PEQ bits 10: graphic EQ - xGEQ bits... -
Page 40: Auto2 - Automode™ Bass Management2 (0X20)
Registers STA309A Channels 1-6 must be arranged via channel mapping (registers CnIM) if necessary in the following manner for this operation: Channel 1: left Channel 2: right Channel 3: left surround Channel 4: right surround Channel 5: center Channel 6: LFE. -
Page 41: Auto3 - Automode™ Am/Prescale/Bass Management Scale (0X21)
STA309A Registers Input channels must be mapped using the channel-mapping feature in the following manner for bass management to be performed properly. 1: left front 2: right front 3: left rear 4: right rear 5: center 6: LFE Table 58. -
Page 42: Preeq - Preset Eq Settings (0X22)
Registers STA309A Table 62. AMAME bits Name Description Automode AM enable AMAME 0: switching frequency determined by PWMS settings 1: switching frequency determined by AMAM settings Table 63. AMAM bits AMAM[2:0] 48 kHz/96 kHz input, fs 44.1 / 88.2 kHz input, fs 0.535 MHz - 0.720 MHz... -
Page 43: Table 65. Peq Bits
STA309A Registers Table 65. PEQ bits PEQ[4:0] Mode / setting 00000 Flat 00001 Rock 00010 Soft Rock 00011 Jazz 00100 Classical 00101 Dance 00110 00111 Soft 01000 Hard 01001 Party 01010 Vocal 01011 Hip-Hop 01100 Dialog 01101 Bass-boost #1 01110... -
Page 44: Ageq - Graphic Eq 80-Hz Band (0X23)
Registers STA309A 7.2.36 AGEQ - graphic EQ 80-Hz band (0x23) Reserved AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0 7.2.37 BGEQ - graphic EQ 300-Hz band (0x24) Reserved BGEQ4 BGEQ3 BGEQ2 BGEQ1 BGEQ0 7.2.38 CGEQ - graphic EQ 1-kHz band (0x25) Reserved CGEQ4... -
Page 45: Biquad Internal Channel Loop-Through (0X28)
STA309A Registers 7.2.41 Biquad internal channel loop-through (0x28) C8BLP C7BLP C6BLP C5BLP C4BLP C3BLP C2BLP C1BLP Each internal processing channel can receive two possible inputs at the input to the biquad block. The input can come either from the output of that channel’s MIX#1 engine or from the output of the bass/treble (Biquad#10) of the previous channel. -
Page 46: Eq Bypass (0X2A)
Registers STA309A 7.2.43 EQ bypass (0x2A) C8EQBP C7EQBP C6EQBP C5EQBP C4EQCBP C3EQBP C2EQBP C1EQBP EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. -
Page 47: Tone Control (0X2C)
STA309A Registers 7.2.45 Tone control (0x2C) TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 This is the tone control boost / cut as a function of BTC and TTC bits. Table 70. BTC and TTC bits BTC[3:0] / TTC[3:0) Boost / cut... -
Page 48: Limiter 1 Attack/Release Threshold (0X30)
0 dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within the STA309A it is possible to exceed 0 dBFS or any other LnAT setting, when this occurs, the limiter, when active, will automatically start reducing the gain. -
Page 49: Table 71. Channel Limiter Mapping
STA309A Registers that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 7. Basic limiter and volume flow diagram Limiter Gain, volume Output Input Saturation Gain Attenuation Table 71. Channel limiter mapping... -
Page 50: Table 73. Release Rate
Registers STA309A Table 73. Release rate LnR[3:0] Release rate (dB/ms) 0000 0.5116 (fast) 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110... -
Page 51: Table 75. Lnrt Bits, Anti-Clipping
STA309A Registers Table 75. LnRT bits, anti-clipping Anti-clipping (AC) LnRT[3:0] (dB relative to FS) -∞ 0000 0001 -29 dB 0010 -20 dB 0011 -16 dB 0100 -14 dB 0101 -12 dB 0110 -10 dB 0111 -8 dB 1000 -7 dB... -
Page 52: Table 77. Lnrt Bits, Dynamic Range Compression
Registers STA309A Table 76. (continued) LnAT bits, dynamic range compression Dynamic range compression (DRC) LnAT[3:0] (dB relative to volume) 1110 1111 Table 77. LnRT bits, dynamic range compression Dynamic range compression (DRC) LnRT[3:0] (db relative to volume + LnAT) 0000 -∞... -
Page 53: Channel 1 And 2 Output Timing (0X33)
STA309A Registers 7.2.53 Channel 1 and 2 output timing (0x33) Reserved C2OT2 C2OT1 C2OT0 Reserved C1OT2 C1OT1 C1OT0 7.2.54 Channel 3 and 4 output timing (0x34) Reserved C4OT2 C4OT1 C4OT0 Reserved C3OT2 C3OT1 C3OT0 7.2.55 Channel 5 and 6 output timing (0x35) -
Page 54: Channel I 2 S Output Mapping Channels 1 And 2 (0X37)
Registers STA309A 7.2.57 Channel I S output mapping channels 1 and 2 (0x37) Reserved C2OM2 C2OM1 C2OM0 Reserved C1OM2 C1OM1 C1OM0 7.2.58 Channel I S output mapping channels 3 and 4 (0x38) Reserved C4OM2 C4OM1 C4OM0 Reserved C3OM2 C3OM1 C3OM0 7.2.59... -
Page 55: Coefficient Address Register 1 (0X3B)
STA309A Registers 7.2.61 Coefficient address register 1 (0x3B) Reserved CFA9 CFA8 7.2.62 Coefficient address register 2 (0x3C) CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0 7.2.63 Coefficient b1 data register, bits 23:16 (0x3D) C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 7.2.64... -
Page 56: Coefficient B2 Data Register, Bits 7:0 (0X42)
Registers STA309A 7.2.68 Coefficient b2 data register, bits 7:0 (0x42) C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0 7.2.69 Coefficient a1 data register, bits 23:16 (0x43) C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16 7.2.70 Coefficient a1 data register, bits 15:8 (0x44) -
Page 57: Coefficient B0 Data Register, Bits 15:8 (0X4A)
7.2.78 Coefficient write control register (0x4C) Reserved Coefficients for EQ and bass management are handled internally in the STA309A via RAM. Access to this RAM is available to the user via an I C register interface. A collection of I C registers are dedicated to this function. -
Page 58: Reading A Coefficient From Ram
Registers STA309A Reading a coefficient from RAM write top 2-bits of address to I C register 0x3B write bottom 8-bits of address to I C register 0x3C read top 8-bits of coefficient in I C address 0x3D read middle 8-bits of coefficient in I... -
Page 59: Writing A Set Of Coefficients To Ram
When using this technique, the 10-bit address would specify the address of the biquad b1 coefficient (for example, decimals 0, 5, 10, 15, …, 100, … 395), and the STA309A will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. -
Page 60: Equalization And Mixing
CxMIX8 Channel 8 Postscale The STA309A provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiply. The scale factor for this multiply is loaded into RAM using the same I C registers as the biquad coefficients and the bass-management. - Page 61 STA309A Equalization and mixing Table 80. RAM block for biquads, mixing, and bass management (continued) Index Index Description Coefficient Default (decimal) (hex) … … … … … 0x31 Channel 1 - Biquad 10 C1HA4 0x400000 0x32 Channel 2 - Biquad 1...
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Page 62: Variable Max Power Correction
Equalization and mixing STA309A Variable max power correction 8.2.1 MPCC1-2 (0x4D, 0x4E) MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. MPCC15 MPCC14 MPCC13... -
Page 63: Pscorrect Registers
STA309A Equalization and mixing PSCorrect registers ADC is used to input ripple data to SDI78. The left channel (7) is used internally. No audio data can therefore be used on these channels. Though all channel mapping and mixing from other inputs to channels 7 and 8 internally are still valid. -
Page 64: Package Mechanical Data
Package mechanical data STA309A Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. -
Page 65: Trademarks And Other Acknowledgements
STA309A Trademarks and other acknowledgements Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. Automode is a trademark of Apogee Technology Inc. Dolby is a registered trademark of Dolby Laboratories. ECOPACK is a registered trademark of STMicroelectronics. -
Page 66: Revision History
Revision history STA309A Revision history Table 81. Document revision history Date Revision Changes Sep-2007 Initial release. Added second order code to Table 1 on page 1 Updated applications schematic in Chapter 6 on page 18 Updated register description and reset value for bit AMPS in... - Page 67 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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