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ST STA309A manual available for free PDF download: Operation Manual
ST STA309A Operation Manual (67 pages)
Multi-channel digital audio processor with DDX
Brand:
ST
| Category:
Computer Hardware
| Size: 0 MB
Table of Contents
Table 1. Device Summary
1
Table of Contents
2
Block Diagram
9
Pin Connections
10
Table 2. Pin Description
10
Electrical Specification
13
Absolute Maximum Ratings
13
Thermal Data
13
Recommended Operating Condition
13
Table 3. Absolute Maximum Ratings
13
Table 4. Thermal Data
13
Table 5. Recommended Operating Condition
13
Electrical Specifications
14
Table 6. General Interface Electrical Specifications
14
Table 7. DC Electrical Characteristics: 3.3-V Buffers
14
Pin Description
15
C Bus Operation
16
Communication Protocol
16
Data Transition or Change
16
Start Condition
16
Stop Condition
16
Data Input
16
Device Addressing
16
Write Operation
17
Byte Write
17
Multi-Byte Write
17
Application Reference Schematic
18
Registers
19
Register Summary
19
Table 8. Register Summary
19
Register Description
22
Configuration Register a (0X00)
22
Table 9. MSC Bits
22
Table 10. MSC Sample Rates
22
Table 11. Interpolation Ratio Bits
23
Table 12. IR Sample Rates
23
Table 13. DSPB Bit
23
Table 14. COS Bits
23
Configuration Register B (0X01) - Serial Input Formats
24
Table 15. SAI Bits
24
Table 16. SAIFB Bit
24
Table 17. SAI and SAIFB Serial Clock
25
Configuration Register C (0X02) - Serial Output Formats
26
Table 18. SAO Bits
26
Table 19. SAOFB Bit
26
Table 20. SAO Serial Clock
26
Configuration Register D (0X03)
27
Table 21. OM Bits
27
Table 22. Output Stage Mode
27
Table 23. CSZ Bits
27
Configuration Register E (0X04)
28
Table 24. CSZ Definition
28
Table 25. MPC Bit
28
Table 26. Cnbo Bits
28
Configuration Register F (0X05)
29
Table 27. HPB Bit
29
Table 28. DRC Bit
29
Table 29. DEMP Bit
29
Table 30. PSL Bit
30
Table 31. BQL Bit
30
Table 32. PWMS Bits
30
Table 33. PWM Output Speed
30
Configuration Register G (0X06)
31
Table 34. Register G Bit Definitions
31
Table 35. AM2E Bit
31
Table 36. HPE Bit
31
Configuration Register H (0X07)
32
Table 37. DCCV Bit
32
Table 38. MPCV Bit
32
Table 39. NSBW Bit
32
Table 40. ZCE Bit
32
Table 41. SVE Bit
32
Table 42. ZDE Bit
32
Configuration Register I (0X08)
33
Table 43. IDE Bit
33
Table 44. BCLE Bit
33
Table 45. LDTE Bit
33
Table 46. ECLE Bit
33
Table 47. PSCE Bit
33
Master Mute Register (0X09)
34
Master Volume Register (0X0A)
34
Channel 1 Volume (0X0B)
34
Channel 2 Volume (0X0C)
34
Channel 3 Volume (0X0D)
34
Channel 4 Volume (0X0E)
34
Table 48. EAPD Bit
34
Channel 5 Volume (0X0F)
35
Channel 6 Volume (0X10)
35
Channel 7 Volume (0X11)
35
Channel 8 Volume (0X12)
35
Channel 1 Volume Trim, Mute, Bypass (0X13)
35
Channel 2 Volume Trim, Mute, Bypass (0X14)
35
Channel 3 Volume Trim, Mute, Bypass (0X15)
35
Channel 4 Volume Trim, Mute, Bypass (0X16)
36
Channel 5 Volume Trim, Mute, Bypass (0X17)
36
Channel 6 Volume Trim, Mute, Bypass (0X18)
36
Channel 7 Volume Trim, Mute, Bypass (0X19)
36
Channel 8 Volume Trim, Mute, Bypass (0X1A)
36
Table 49. MV Bits
37
Table 50. Cnv Bits
37
Table 51. Cnvt Bits
37
Channel Input Mapping Channels 1 and 2 (0X1B)
38
Channel Input Mapping Channels 3 and 4 (0X1C)
38
Channel Input Mapping Channels 5 and 6 (0X1D)
38
Channel Input Mapping Channels 7 and 8 (0X1E)
38
Table 52. Cnim Bits
38
AUTO1 - Automode™ EQ, Volume, GC (0X1F)
39
Table 53. AMEQ Bits
39
Table 54. AMV Bits
39
Table 55. AMDM Bit
39
AUTO2 - Automode™ Bass Management2 (0X20)
40
Table 56. AMBMME Bit
40
Table 57. AMBMXE Bit
40
AUTO3 - Automode™ Am/Prescale/Bass Management Scale (0X21)
41
Table 58. CSS and RSS Bits
41
Table 59. FSS and SUB Bits
41
Table 60. AMPS Bit
41
Table 61. MSA Bit
41
PREEQ - Preset EQ Settings (0X22)
42
Table 62. AMAME Bits
42
Table 63. AMAM Bits
42
Table 64. XO Bits
42
Table 65. PEQ Bits
43
AGEQ - Graphic EQ 80-Hz Band (0X23)
44
BGEQ - Graphic EQ 300-Hz Band (0X24)
44
CGEQ - Graphic EQ 1-Khz Band (0X25)
44
DGEQ - Graphic EQ 3-Khz Band (0X26)
44
EGEQ - Graphic EQ 8-Khz Band (0X27)
44
Table 66. Xgeq Bits
44
Biquad Internal Channel Loop-Through (0X28)
45
MIX Internal Channel Loop-Through (0X29)
45
Table 67. Cnblp Bits
45
Table 68. Cnmxlp Bits
45
EQ Bypass (0X2A)
46
Tone Control Bypass (0X2B)
46
Table 69. Cneqbp Bits
46
Tone Control (0X2C)
47
Channel Limiter Select Channels 1,2,3,4 (0X2D)
47
Channel Limiter Select Channels 5,6,7,8 (0X2E)
47
Limiter 1 Attack/Release Rate (0X2F)
47
Table 70. BTC and TTC Bits
47
Limiter 1 Attack/Release Threshold (0X30)
48
Limiter 2 Attack/Release Rate (0X31)
48
Limiter 2 Attack/Release Threshold (0X32)
48
Bit Description
48
Table 71. Channel Limiter Mapping
49
Table 72. Attack Rate
49
Table 73. Release Rate
50
Table 74. Lnat Bits, Anti-Clipping
50
Table 75. Lnrt Bits, Anti-Clipping
51
Table 76. Lnat Bits, Dynamic Range Compression
51
Table 77. Lnrt Bits, Dynamic Range Compression
52
Channel 1 and 2 Output Timing (0X33)
53
Channel 3 and 4 Output Timing (0X34)
53
Channel 5 and 6 Output Timing (0X35)
53
Channel 7 and 8 Output Timing (0X36)
53
Table 78. PWM Slot
53
Channel I 2 S Output Mapping Channels 1 and 2 (0X37)
54
Channel I 2 S Output Mapping Channels 3 and 4 (0X38)
54
Channel I 2 S Output Mapping Channels 5 and 6 (0X39)
54
Channel I 2 S Output Mapping Channels 7 and 8 (0X3A)
54
Table 79. Cnom Serial Output
54
Coefficient Address Register 1 (0X3B)
55
Coefficient Address Register 2 (0X3C)
55
Coefficient B1 Data Register, Bits 23:16 (0X3D)
55
Coefficient B1 Data Register, Bits 15:8 (0X3E)
55
Coefficient B1 Data Register, Bits 7:0 (0X3F)
55
Coefficient B2 Data Register, Bits 23:16 (0X40)
55
Coefficient B2 Data Register, Bits 15:8 (0X41)
55
Coefficient B2 Data Register, Bits 7:0 (0X42)
56
Coefficient A1 Data Register, Bits 23:16 (0X43)
56
Coefficient A1 Data Register, Bits 15:8 (0X44)
56
Coefficient A1 Data Register, Bits 7:0 (0X45)
56
Coefficient A2 Data Register, Bits 23:16 (0X46)
56
Coefficient A2 Data Register, Bits 15:8 (0X47)
56
Coefficient A2 Data Register, Bits 7:0 (0X48)
56
Coefficient B0 Data Register, Bits 23:16 (0X49)
56
Coefficient B0 Data Register, Bits 15:8 (0X4A)
57
Coefficient B0 Data Register, Bits 7:0 (0X4B)
57
Coefficient Write Control Register (0X4C)
57
Reading a Coefficient from RAM
58
Reading a Set of Coefficients from RAM
58
Writing a Single Coefficient to RAM
58
Writing a Set of Coefficients to RAM
59
Equalization and Mixing
60
Postscale
60
Table 80. RAM Block for Biquads, Mixing, and Bass Management
60
Variable Max Power Correction
62
MPCC1-2 (0X4D, 0X4E)
62
Variable Distortion Compensation
62
DCC1-2 (0X4F, 0X50)
62
Pscorrect Registers
63
PSC1-2: Ripple Correction Value (RCV) (0X51, 0X52)
63
PSC3: Correction Normalization Value (CNV) (0X53)
63
Package Mechanical Data
64
Trademarks and Other Acknowledgements
65
Revision History
66
Table 81. Document Revision History
66
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