Analog Output Channels; Analog Output Phase; External Trigger Input; External Clock Input - 4DSP FMC230 User Manual

UM023 FMC230 User Manual
r1.11

4.4 Analog output channels

The DAC output circuit is constructed such that different build options are available. The
default configuration is a wideband balun ETC1-1-13 (MACOM; 4.5 to 3000MHz) as shown in
Figure 4. This configuration is the recommended output circuit for mixed-mode operation of the
DAC, for details refer to the AD9129 datasheet.. Please contact 4DSP for custom
configurations.

4.4.1 Analog output phase

While not intuitively obvious from the representative schematic below, the analog output
voltage tracks the data written to the DAC. The analog output signal at its maximum when the
DAC is set to full scale.
As shown in the schematic, the analog output connector X8 is directly connected to the DACs
IOUTN (labeled DAC1_IN) signal thru the balun T4, this results in the output voltage tracking
the voltage on the IOUTN pin.
From the perspective of the output connector and IOUTN, the analog output is formed by a
voltage divider consisting of the high side pulled up to +1.8V by R89 and L13, and the low side
pulled down to -1.5V by the DACs programmable current source.
When 0x0000 is written to the DAC, IOUTN will be sourcing its maximum current thru the
pullups resulting in a negative output voltage.
When the full scale value is written to the DAC, the current thru IOUTN and the pullups will be
at its minimum resulting in the maximum positive voltage on the output.
The complementary output signal IOUTP performs in a similar manner except that it is 180
degrees out of phase with the value written to the DAC, The IOUTP and IOUTN signals are
combined by the transformer action of the balun T4.
Figure 4: Wideband balun output option

4.5 External trigger input

An external trigger is available on the front panel (MMCX connector). The trigger signal
connects to a buffer (NB6N11S) before being sent to the carrier card. The buffer translates the
external LVTTL signal to LVDS and connects to the FMC connector. The trigger input is
terminated to ground with 4.7kΩ.

4.6 External clock input

There is one MMCX clock input on the front panel that can serve as sampling clock input.
Refer also to section 4.9 for more information about the clock tree.
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