Appendix Bcpld Register Map; Release - 4DSP FMC230 User Manual

UM023 FMC230 User Manual
Appendix B
Register
0x00
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 6..5
Bit 7
0x01
Bit 0
R/O Bit 1
R/O Bit 2
Bit 3
R/O Bit 4
R/O Bit 5
Bit 6
Bit 7
0x02
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 7..5
UM023
CPLD Register map
Control register 0
'0' for internal reference clock
'1' for external reference clock (disable internal reference)
Reserved
'0' Release DAC reset
'1' Assert DAC reset
'0' Release CLK reset (AD9517)
'1' Assert CLK reset (AD9517)
'0' Release CLK sync (AD9517)
'1' Assert CLK sync (AD9517)
Reserved
EEPROM write enable. Recommended to write '0'.
Control register 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
'0' for CLK power enable (AD9517)
'1' for CLK power down (AD9517)
'0' for MONITORING power enable (AD7291 rst_l)
'1' for MONITORING power down (AD7291 rst_l)
Status register
REFMON (AD9517)
LD (AD9517)
STATUS (AD9517)
ALERT (AD7291)
IRQ (DAC)
CPLD revision (current = b'001')
Table 9: CPLD Register Map
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Description
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