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Summary of Contents for 4DSP FMC230
- Page 1 FMC230 User Manual 4DSP, USA www.4dsp.com/forum This document is the property of 4DSP LLC. and may not be copied nor communicated to a third party without the written permission of 4DSP LLC. © 4DSP LLC 2015 UM023 www.4dsp.com - 1 -...
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Page 2: Revision History
UM023 FMC230 User Manual r1.11 Revision History Date Description Revision 2012-12-19 Release 2013-02-05 Corrected pin assignments in Appendix A 2013-03-22 Updated analog output range in Table 2 and added a FMC700 requirement information for KC705 2013-08-15 Updated analog output bandwidth in Table 2. Added a signal description in Appendix A. -
Page 3: Table Of Contents
UM023 FMC230 User Manual r1.11 Table of Contents Acronyms and related documents ................4 Acronyms ........................4 Related Documents ....................4 General description ......................5 Installation ........................5 Requirements and handling instructions ..............5 Design ..........................6 Physical specifications ....................6 4.1.1... -
Page 4: Acronyms And Related Documents
UM023 FMC230 User Manual r1.11 1 Acronyms and related documents 1.1 Acronyms Analog-to-Digital Converter Double Data Rate Digital Signal Processing EPROM Erasable Programmable Read-Only Memory FBGA Fineline Ball Grid Array FPGA Mezzanine Card FPGA Field Programmable Gate Array JTAG Join Test Action Group... -
Page 5: General Description
2 General description The FMC230 is a two channel DAC FMC daughter card. The card provides two 14-bit up to 5.7 GSPS DAC channels which can be clocked by an internal clock source (optionally locked to an external reference) or an externally supplied sample clock. There is one trigger input for customized sampling control. -
Page 6: Design
UM023 FMC230 User Manual r1.11 4 Design 4.1 Physical specifications 4.1.1 Board Dimensions The FMC card complies with the FMC standard known as ANSI/VITA 57.1. The card is a single-width, conduction-cooled mezzanine module (with region 1 and front panel I/O). There may be a mechanical conflict with the front rib on a carrier card. -
Page 7: Jtag
UM023 FMC230 User Manual r1.11 FMC Top Connector The top connector is the main connector to the FMC carrier board. The pin-out is defined in the appendix. The connector is a HPC connector. FMC Bottom Connector The high-pin count connector enables FMC card stacking. The following connections are available between the top and bottom FMC connector: ... - Page 8 Frequency range Internal sampling clock Format LVPECL DAC: up to 5300MHz (Software selectable, contact 4DSP for Frequency Range frequencies higher frequencies up to 5700MHz) Table 2 : FMC daughter card main characteristics 3.3V LVTTL into 50Ohm would result in 14dBm, a 1A Schottky diode in the clock input circuit protects the clock input from overvoltage when driving the input with a LVTTL signal.
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Page 9: Analog Output Channels
ETC1-1-13 (MACOM; 4.5 to 3000MHz) as shown in Figure 4. This configuration is the recommended output circuit for mixed-mode operation of the DAC, for details refer to the AD9129 datasheet.. Please contact 4DSP for custom configurations. -
Page 10: External Reference Input
UM023 FMC230 User Manual r1.11 Note: When internal clock is enabled and there is no need for an external reference, it is highly recommended to leave the clock input unconnected to prevent interference with the internal clock. 4.7 External reference input There is one MMCX reference input on the front panel that can serve as reference clock input. -
Page 11: Pll Design
UM023 FMC230 User Manual r1.11 Loop Filter TCXO REF_EN 30.72MHz Clock DAC 0 DAC 1 To FMC To GBT To OUT Figure 5: Clock tree The AD9517 has four LVPECL outputs. OUT2 and OUT3 are used for clocking the DAC devices. -
Page 12: Power Supply
UM023 FMC230 User Manual r1.11 Card Type Device VCO Range DAC Clock FMC230 AD9517-1 2300MHz - 2650MHz 2457.60MHz 2457.60MHz Table 3: FMC default clock configurations Note: Higher DAC clock frequencies (2850MHz for sampling up to 5700Msps) can be achieved using external clock. -
Page 13: Controlling The Fmc230
UM023 FMC230 User Manual r1.11 ADP2301 ADP7182 22mA @ 12V 45mW 120mA @ -1.5V 48mW (Eff. 85%) Max. 200mA 330mA @ 1.8Vd ADP151 AD9129 175mA @ 1.8Va 263mW 850mW 60mA @ -1.5Va Total Power ADP1753 660mA @ 1.8V Consumption: 990mW +/- 5.6W... - Page 14 UM023 FMC230 User Manual r1.11 3.3V VADJ CPLD FMC Connector ADG3304 FMC_TO_CPLD[3..0] Signals to: 3.3V AD9517 BANK Signals to: 1.8V BANK AD9129 Figure 8: FMC control interface The FMC is controlled from the carrier hardware through a single SPI communication bus. The SPI communication bus is connected to a CPLD which has the following tasks: ...
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Page 15: Spi Programming
UM023 FMC230 User Manual r1.11 Local Side CPLD FMC Side DAC0_N_CS DAC1_N_CS CLK_N_CS FMC_TO_CPLD(0) SCLK FMC_TO_CPLD(1) SCLK N_CS FMC_TO_CPLD(2) SDIO SDIO Shift register REF_EN SRC_SEL Ctrl DAC_RST REG0 CLK_N_RESET REG1 REG2 REFMON FMC_TO_CPLD(3) STATUS N_INT ALERT Figure 9: CPLD architecture Notes: ... - Page 16 UM023 FMC230 User Manual r1.11 N_CS SCLK SDIO P0 R/W A6 8-bit pre-selection 8-bit instruction 8-bit register data Figure 10: Write instruction to CPLD registers A1:A0 N_CS SCLK SDIO P0 R/W A6 8-bit pre-selection 8-bit instruction 8-bit register data Figure 11: Read instruction to CPLD registers A1:A0...
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Page 17: Environment
UM023 FMC230 User Manual r1.11 N_CS SCLK SDIO P0 R/W W1 W0 A12 A11 A10 A9 8-bit pre-selection 16-bit instruction 8-bit register data Figure 15: Read instruction to AD9517 registers A12:A0 6 Environment 6.1 Temperature Operating temperature ° °... -
Page 18: Cooling
For standalone operations (such as on a Xilinx development kit), it is highly recommended to blow air across the FMC and ensure that the temperature of the devices is within the allowed range. 4DSP’s warranty does not cover boards on which the maximum allowed temperature has been exceeded. -
Page 19: Ordering Information
UM023 FMC230 User Manual r1.11 9 Ordering information Part Number: FMC230-2-1-1-1 Card Type Temperature Range Industrial (-40 C to +85 C) = 1 Commercial (0 C to +70 C) = 2 Connector Type MMCX (Standard feature) = 1 SSMC = 2... -
Page 20: Appendix Alpc / Hpc Pin-Out
UM023 FMC230 User Manual r1.10 Appendix A LPC / HPC pin-out Note that FMC700 is required to use the FMC230 on KC705 AV57.1 HPC Pin FMC230 Signal AV57.1 HPC Pin FMC230 Signal AV57.1 HPC Pin FMC230 Signal CLK0_M2C_N CLK_TO_FPGA_N... - Page 21 UM023 FMC230 User Manual r1.11 LA18_N_CC DAC0_P1_DP01_N HA22_N LA18_P_CC DAC0_P1_DP01_P HA22_P LA19_N DAC0_P1_DP03_N HA23_N LA19_P DAC0_P1_DP03_P HA23_P LA20_N DAC0_P1_DP02_N LA20_P DAC0_P1_DP02_P LA21_N DAC0_P1_DP05_N LA21_P DAC0_P1_DP05_P LA22_N DAC0_P1_DP04_N LA22_P DAC0_P1_DP04_P LA23_N DAC0_P1_DP06_N LA23_P DAC0_P1_DP06_P LA24_N DAC0_P1_DP10_N LA24_P DAC0_P1_DP10_P LA25_N DAC0_P1_DP09_N LA25_P...
- Page 22 Power good indicator from carrier to PG_C2M STATUS Input LVTTL module. Power good indicator from module to PG_M2C STATUS Output LVTTL carrier. I2C_SCL Input LVTTL I2C clock line. I2C_SDA Bidir LVTTL I2C data line. Table 8: FMC230 Signal Description UM023 www.4dsp.com - 22...
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Page 23: Appendix Bcpld Register Map
UM023 FMC230 User Manual r1.11 Appendix B CPLD Register map Description Register 0x00 Control register 0 ‘0’ for internal reference clock Bit 0 ‘1’ for external reference clock (disable internal reference) Bit 1 Reserved ‘0’ Release DAC reset Bit 2 ‘1’...