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UM023 FMC230 User Manual
4 Design
4.1 Physical specifications
4.1.1 Board Dimensions
The FMC card complies with the FMC standard known as ANSI/VITA 57.1. The card is a
single-width, conduction-cooled mezzanine module (with region 1 and front panel I/O). There
may be a mechanical conflict with the front rib on a carrier card. The stacking height is 10mm,
and the PCB thickness is 1.6mm.
4.1.2 Front panel
There are six MMCX connectors available from the front panel. From top to bottom:
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Analog outputs B (D1) and A (D0)
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Trigger in (TR)
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Clock Input (CI)
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Reference Input (RI)
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Clock Output (CO)
4.2 Electrical specifications
The DAC devices use DDR LVDS signals mapped to the regular FMC pins. Each channel has
two 14-bit wide DDR LVDS busses.
Control signals operate in LVCMOS mode. A VADJ range of 1.2V to 3.3V is supported. The
voltage on VIO_B pins will follow the voltage on VADJ.
The CLKx pins are required to be LVDS by the FMC standard. CLK2 and CLK3 are not used
for best compatibility with Xilinx development platforms. CLK0 is connected to a spare clock
output of the clock tree. CLK1 is connected to the external trigger.
4.2.1 EEPROM
The FMC card has a small serial EEPROM (M24C02) which is accessible from the carrier card
2
through the I
C bus. The EEPROM is powered by 3P3VAUX. The standby current is only
0.01µA when SCL and SDA are kept at 3P3VAUX level. These signals may also be left
floating since pull-up resistors are present on the FMC. The EEPROM is write-protected by
default.
4.2.1 FMC Connector
UM023
Figure 2: Front panel layout
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